From 0954ee7fa9ffb09f8519541bebe2373ec98f6795 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung
Date: Thu, 27 Aug 2020 12:53:07 +0800
Subject: [PATCH] Add SD instruction
---
rvfi/insns/insn_sd.py | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 rvfi/insns/insn_sd.py
diff --git a/rvfi/insns/insn_sd.py b/rvfi/insns/insn_sd.py
new file mode 100644
index 0000000..74e9762
--- /dev/null
+++ b/rvfi/insns/insn_sd.py
@@ -0,0 +1,42 @@
+from .insn import *
+
+"""
+SD instruction
+"""
+
+class InsnSd(Insn):
+ def elaborate(self, platform):
+ m = super().elaborate(platform)
+
+ m.d.comb += self.insn_imm.eq(Value.as_signed(Cat(self.rvfi_insn[7:12], self.rvfi_insn[25:32])))
+
+ if self.params.csr_misa:
+ m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
+ m.d.comb += self.spec_csr_misa_rmask.eq(0)
+ else:
+ m.d.comb += self.misa_ok.eq(1)
+
+ if self.params.aligned_mem:
+ addr = Signal(self.params.xlen)
+ m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0100011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+ m.d.comb += self.spec_mem_addr.eq(addr & ~(self.params.xlen // 8 - 1))
+ m.d.comb += self.spec_mem_wmask.eq(((1 << 8) - 1) << (addr - self.spec_mem_addr))
+ m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata << (8 * (addr - self.spec_mem_addr)))
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+ m.d.comb += self.spec_trap.eq(((addr & (8 - 1)) != 0) | ~self.misa_ok)
+ else:
+ addr = Signal(self.params.xlen)
+ m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
+ m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0100011))
+ m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
+ m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
+ m.d.comb += self.spec_mem_addr.eq(addr)
+ m.d.comb += self.spec_mem_wmask.eq((1 << 8) - 1)
+ m.d.comb += self.spec_mem_wdata.eq(self.rvfi_rs2_rdata)
+ m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
+ m.d.comb += self.spec_trap.eq(~self.misa_ok)
+
+ return m