riscv-formal-nmigen/rvfi/insns/insn_srlw.py

from .insn_rv64i_r_type import *

"""
SRLW instruction
"""

class InsnSrlw(InsnRV64IRType):
    def __init__(self, params):
        super().__init__(params, 0b0000000, 0b101)

    def elaborate(self, platform):
        m = super().elaborate(platform)

        result = Signal(32)
        m.d.comb += result.eq(self.rvfi_rs1_rdata[:32] >> self.rvfi_rs2_rdata[:5])
        m.d.comb += spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))

        return m