2020-08-28 11:52:09 +08:00
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from .insn_rv64m_r_type import *
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"""
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DIVW instruction
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"""
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class InsnDivw(InsnRV64MRType):
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def __init__(self, params):
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2020-08-28 12:20:56 +08:00
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super().__init__(params, 0b100)
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2020-08-28 12:30:39 +08:00
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2020-08-28 11:52:09 +08:00
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def elaborate(self, platform):
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m = super().elaborate(platform)
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result = Signal(32)
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if self.params.altops:
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m.d.comb += result.eq((self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ 0x29bbf66f7f8529ec)
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else:
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m.d.comb += result.eq(Mux(self.rvfi_rs2_rdata[:32] == 0, 2 ** 32 - 1, Mux((self.rvfi_rs1_rdata == (1 << 31)) & (self.rvfi_rs2_rdata == 2 ** 32 - 1), 1 << 31, Value.as_signed(self.rvfi_rs1_rdata[:32]) // Value.as_signed(self.rvfi_rs2_rdata[:32]))))
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Mux(result[31], 2 ** (self.params.xlen - 32) - 1, 0) << 32) | result, 0))
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return m
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