riscv-formal-nmigen/rvfi/insns/insn_add.py

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from .insn_rv32i_r_type import *
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"""
ADD instruction
"""
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class InsnAdd(InsnRV32IRType):
def __init__(self, params):
super().__init__(params, 0b0000000, 0b000, 0b0110011)
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def elaborate(self, platform):
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m = super().elaborate(platform)
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m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata + self.rvfi_rs2_rdata, 0))
return m