A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

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README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Breakdown

File/Directory	Description
`shell.nix`	nix-shell configuration file
`rvfi`	RISC-V Formal Verification Framework (nMigen port)
`rvfi/insns`	Supported RISC-V instructions and ISAs
`rvfi/checks`	Checks for RISC-V compliant cores
`rvfi/cores`	Cores currently tested against this port of riscv-formal
`rvfi/cores/minerva/verify.py`	Verification tasks for the Minerva core

Running the Verification

First make sure you have Nix installed. Then cd to the root directory of this repo and run:

$ nix-shell

This should run the tests (cache, multiplier, divider) provided by Minerva itself and give you an environment with all the dependencies required for this project. Then, to run the main verification tasks for Minerva provided in this repo:

$ python -m rvfi.cores.minerva.verify

Note that a pool of # of cores on your machine processes is created by default which enables the verification tasks to execute in parallel. The number of processes in the pool can be configured by passing in a command-line argument, e.g.

$ python -m rvfi.cores.minerva.verify 8

creates a pool of 8 processes.

Scope

The RV32I, RV32M, RV64I and RV64M ISAs are currently implemented but only RV32IM are being tested by integrating with the Minerva core.

License

See LICENSE