riscv-formal-nmigen/rvfi/checks/insn_check.py

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from nmigen import *
from nmigen.asserts import *
"""
Instruction Check
"""
class InsnCheck(Elaboratable):
def __init__(self, params, insn_model, rvformal_addr_valid):
# Core-specific parameters
self.params = params
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# ISA under test
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self.insn_model = insn_model
# Address validity and equality
self.rvformal_addr_valid = rvformal_addr_valid
self.rvformal_addr_eq = lambda a, b: (self.rvformal_addr_valid(a) == self.rvformal_addr_valid(b)) & ((~self.rvformal_addr_valid(a)) | (a == b))
# Input ports
self.reset = Signal(1)
self.check = Signal(1)
self.rvfi_valid = Signal(1)
self.rvfi_order = Signal(64)
self.rvfi_insn = Signal(self.params.ilen)
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self.rvfi_trap = Signal(1)
self.rvfi_halt = Signal(1)
self.rvfi_intr = Signal(1)
self.rvfi_mode = Signal(2)
self.rvfi_ixl = Signal(2)
self.rvfi_rs1_addr = Signal(5)
self.rvfi_rs2_addr = Signal(5)
self.rvfi_rs1_rdata = Signal(self.params.xlen)
self.rvfi_rs2_rdata = Signal(self.params.xlen)
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self.rvfi_rd_addr = Signal(5)
self.rvfi_rd_wdata = Signal(self.params.xlen)
self.rvfi_pc_rdata = Signal(self.params.xlen)
self.rvfi_pc_wdata = Signal(self.params.xlen)
self.rvfi_mem_addr = Signal(self.params.xlen)
self.rvfi_mem_rmask = Signal(int(self.params.xlen // 8))
self.rvfi_mem_wmask = Signal(int(self.params.xlen // 8))
self.rvfi_mem_rdata = Signal(self.params.xlen)
self.rvfi_mem_wdata = Signal(self.params.xlen)
if self.params.csr_misa:
self.rvfi_csr_misa_rmask = Signal(self.params.xlen)
self.rvfi_csr_misa_wmask = Signal(self.params.xlen)
self.rvfi_csr_misa_rdata = Signal(self.params.xlen)
self.rvfi_csr_misa_wdata = Signal(self.params.xlen)
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def ports(self):
input_ports = [
self.reset,
self.check,
self.rvfi_valid,
self.rvfi_order,
self.rvfi_insn,
self.rvfi_trap,
self.rvfi_halt,
self.rvfi_intr,
self.rvfi_mode,
self.rvfi_ixl,
self.rvfi_rs1_addr,
self.rvfi_rs2_addr,
self.rvfi_rs1_rdata,
self.rvfi_rs2_rdata,
self.rvfi_rd_addr,
self.rvfi_rd_wdata,
self.rvfi_pc_rdata,
self.rvfi_pc_wdata,
self.rvfi_mem_addr,
self.rvfi_mem_rmask,
self.rvfi_mem_wmask,
self.rvfi_mem_rdata,
self.rvfi_mem_wdata
]
if self.params.csr_misa:
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input_ports.extend([
self.rvfi_csr_misa_rmask,
self.rvfi_csr_misa_wmask,
self.rvfi_csr_misa_rdata,
self.rvfi_csr_misa_wdata
])
return input_ports
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def elaborate(self, platform):
m = Module()
valid = Signal(1)
m.d.comb += valid.eq((~self.reset) & self.rvfi_valid)
insn = self.rvfi_insn
trap = self.rvfi_trap
halt = self.rvfi_halt
intr = self.rvfi_intr
rs1_addr = self.rvfi_rs1_addr
rs2_addr = self.rvfi_rs2_addr
rs1_rdata = self.rvfi_rs1_rdata
rs2_rdata = self.rvfi_rs2_rdata
rd_addr = self.rvfi_rd_addr
rd_wdata = self.rvfi_rd_wdata
pc_rdata = self.rvfi_pc_rdata
pc_wdata = self.rvfi_pc_wdata
mem_addr = self.rvfi_mem_addr
mem_rmask = self.rvfi_mem_rmask
mem_wmask = self.rvfi_mem_wmask
mem_rdata = self.rvfi_mem_rdata
mem_wdata = self.rvfi_mem_wdata
if self.params.csr_misa:
csr_misa_rdata = self.rvfi_csr_misa_rdata
csr_misa_rmask = self.rvfi_csr_misa_rmask
spec_csr_misa_rmask = Signal(self.params.xlen)
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spec_valid = Signal(1)
spec_trap = Signal(1)
spec_rs1_addr = Signal(5)
spec_rs2_addr = Signal(5)
spec_rd_addr = Signal(5)
spec_rd_wdata = Signal(self.params.xlen)
spec_pc_wdata = Signal(self.params.xlen)
spec_mem_addr = Signal(self.params.xlen)
spec_mem_rmask = Signal(int(self.params.xlen // 8))
spec_mem_wmask = Signal(int(self.params.xlen // 8))
spec_mem_wdata = Signal(self.params.xlen)
rs1_rdata_or_zero = Signal(self.params.xlen)
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m.d.comb += rs1_rdata_or_zero.eq(Mux(spec_rs1_addr != 0, rs1_rdata, 0))
rs2_rdata_or_zero = Signal(self.params.xlen)
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m.d.comb += rs2_rdata_or_zero.eq(Mux(spec_rs2_addr != 0, rs2_rdata, 0))
m.submodules.insn_spec = insn_spec = self.insn_model(self.params)
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m.d.comb += insn_spec.rvfi_valid.eq(valid)
m.d.comb += insn_spec.rvfi_insn.eq(insn)
m.d.comb += insn_spec.rvfi_pc_rdata.eq(pc_rdata)
m.d.comb += insn_spec.rvfi_rs1_rdata.eq(rs1_rdata_or_zero)
m.d.comb += insn_spec.rvfi_rs2_rdata.eq(rs2_rdata_or_zero)
m.d.comb += insn_spec.rvfi_mem_rdata.eq(mem_rdata)
if self.params.csr_misa:
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m.d.comb += insn_spec.rvfi_csr_misa_rdata.eq(csr_misa_rdata)
m.d.comb += spec_csr_misa_rmask.eq(insn_spec.spec_csr_misa_rmask)
m.d.comb += spec_valid.eq(insn_spec.spec_valid)
m.d.comb += spec_trap.eq(insn_spec.spec_trap)
m.d.comb += spec_rs1_addr.eq(insn_spec.spec_rs1_addr)
m.d.comb += spec_rs2_addr.eq(insn_spec.spec_rs2_addr)
m.d.comb += spec_rd_addr.eq(insn_spec.spec_rd_addr)
m.d.comb += spec_rd_wdata.eq(insn_spec.spec_rd_wdata)
m.d.comb += spec_pc_wdata.eq(insn_spec.spec_pc_wdata)
m.d.comb += spec_mem_addr.eq(insn_spec.spec_mem_addr)
m.d.comb += spec_mem_rmask.eq(insn_spec.spec_mem_rmask)
m.d.comb += spec_mem_wmask.eq(insn_spec.spec_mem_wmask)
m.d.comb += spec_mem_wdata.eq(insn_spec.spec_mem_wdata)
insn_pma_x = Signal(1)
mem_pma_r = Signal(1)
mem_pma_w = Signal(1)
mem_log2len = Signal(2)
m.d.comb += mem_log2len.eq(Mux((spec_mem_rmask | spec_mem_wmask) & 0b11110000, 3, Mux((spec_mem_rmask | spec_mem_wmask) & 0b00001100, 2, Mux((spec_mem_rmask | spec_mem_wmask) & 0b00000010, 1, 0))))
m.d.comb += insn_pma_x.eq(1)
m.d.comb += mem_pma_r.eq(1)
m.d.comb += mem_pma_w.eq(1)
mem_access_fault = Signal(1)
m.d.comb += mem_access_fault.eq((spec_mem_rmask & ~mem_pma_r) | (spec_mem_wmask & ~mem_pma_w) | ((spec_mem_rmask | spec_mem_wmask) & ~self.rvformal_addr_valid(spec_mem_addr)))
with m.If(~self.reset):
m.d.comb += Cover(spec_valid)
m.d.comb += Cover(spec_valid & ~trap)
m.d.comb += Cover(self.check & spec_valid)
m.d.comb += Cover(self.check & spec_valid & ~trap)
with m.If((~self.reset) & self.check):
m.d.comb += Assume(spec_valid)
with m.If((~self.rvformal_addr_valid(pc_rdata)) | (~insn_pma_x) | mem_access_fault):
m.d.comb += Assert(trap)
m.d.comb += Assert(rd_addr == 0)
m.d.comb += Assert(rd_wdata == 0)
m.d.comb += Assert(mem_wmask == 0)
with m.Else():
if self.params.csr_misa:
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m.d.comb += Assert((spec_csr_misa_rmask & csr_misa_rmask) == spec_csr_misa_rmask)
with m.If(rs1_addr == 0):
m.d.comb += Assert(rs1_rdata == 0)
with m.If(rs2_addr == 0):
m.d.comb += Assert(rs2_rdata == 0)
with m.If(~spec_trap):
with m.If(spec_rs1_addr != 0):
m.d.comb += Assert(spec_rs1_addr == rs1_addr)
with m.If(spec_rs2_addr != 0):
m.d.comb += Assert(spec_rs2_addr == rs2_addr)
m.d.comb += Assert(spec_rd_addr == rd_addr)
m.d.comb += Assert(spec_rd_wdata == rd_wdata)
m.d.comb += Assert(self.rvformal_addr_eq(spec_pc_wdata, pc_wdata))
with m.If(spec_mem_wmask | spec_mem_rmask):
m.d.comb += Assert(self.rvformal_addr_eq(spec_mem_addr, mem_addr))
for i in range(int(self.params.xlen // 8)):
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with m.If(spec_mem_wmask[i]):
m.d.comb += Assert(mem_wmask[i])
m.d.comb += Assert(spec_mem_wdata[i*8:i*8+8] == mem_wdata[i*8:i*8+8])
with m.Elif(mem_wmask[i]):
m.d.comb += Assert(mem_rmask[i])
m.d.comb += Assert(mem_rdata[i*8:i*8+8] == mem_wdata[i*8:i*8+8])
with m.If(spec_mem_rmask[i]):
m.d.comb += Assert(mem_rmask[i])
m.d.comb += Assert(spec_trap == trap)
return m