artiq/artiq/gateware/serwb
Florent Kermarrec 64c8eee28d serwb/phy/master: fix slave ready detection by filtering possible glitches on rx data (seems to happen when RTM fpga is not loaded) 2018-04-30 23:59:56 +02:00
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__init__.py gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window 2017-08-30 14:40:11 +02:00
core.py serwb/core/phy: move scrambler in phy, add link test, revert delay min/max checks 2018-04-17 19:21:21 +02:00
etherbone.py gateware/serwb: cleanup imports, use buffered SyncFIFO in EtherboneRecordSender 2017-11-03 12:15:14 +01:00
kusphy.py serwb/phys: remove phy_width (revert linerate to 1Gbps) 2018-04-17 19:19:18 +02:00
packet.py gateware/serwb: cleanup packet 2018-01-03 17:30:12 +01:00
phy.py serwb/phy/master: fix slave ready detection by filtering possible glitches on rx data (seems to happen when RTM fpga is not loaded) 2018-04-30 23:59:56 +02:00
s7phy.py serwb/phys: remove phy_width (revert linerate to 1Gbps) 2018-04-17 19:19:18 +02:00
scrambler.py serwb/scrambler: dynamic enable/disable 2018-04-17 19:20:06 +02:00