mirror of https://github.com/m-labs/artiq.git
38 lines
1.1 KiB
Python
38 lines
1.1 KiB
Python
from migen import *
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from misoc.interconnect import stream
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from artiq.gateware.serwb.packet import Packetizer, Depacketizer
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from artiq.gateware.serwb.etherbone import Etherbone
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class SERWBCore(Module):
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def __init__(self, phy, clk_freq, mode):
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# etherbone
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self.submodules.etherbone = etherbone = Etherbone(mode)
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# packetizer / depacketizer
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depacketizer = Depacketizer(clk_freq)
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packetizer = Packetizer()
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self.submodules += depacketizer, packetizer
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# fifos
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tx_fifo = stream.SyncFIFO([("data", 32)], 16)
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rx_fifo = stream.SyncFIFO([("data", 32)], 16)
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self.submodules += tx_fifo, rx_fifo
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# modules connection
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self.comb += [
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# core --> phy
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packetizer.source.connect(tx_fifo.sink),
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tx_fifo.source.connect(phy.sink),
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# phy --> core
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phy.source.connect(rx_fifo.sink),
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rx_fifo.source.connect(depacketizer.sink),
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# etherbone <--> core
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depacketizer.source.connect(etherbone.sink),
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etherbone.source.connect(packetizer.sink)
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]
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