mirror of https://github.com/m-labs/artiq.git
114 lines
3.2 KiB
Python
114 lines
3.2 KiB
Python
from functools import reduce
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from operator import xor
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from migen import *
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from misoc.interconnect import stream
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def K(x, y):
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return (y << 5) | x
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@ResetInserter()
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@CEInserter()
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class _Scrambler(Module):
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def __init__(self, n_io, n_state=23, taps=[17, 22]):
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self.i = Signal(n_io)
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self.o = Signal(n_io)
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# # #
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state = Signal(n_state, reset=1)
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(n_io)):
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flip = reduce(xor, [curval[tap] for tap in taps])
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self.comb += self.o[i].eq(flip ^ self.i[i])
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curval.insert(0, flip)
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curval.pop()
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self.sync += state.eq(Cat(*curval[:n_state]))
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class Scrambler(Module):
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def __init__(self, sync_interval=1024):
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self.enable = Signal()
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self.sink = sink = stream.Endpoint([("data", 32)])
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self.source = source = stream.Endpoint([("d", 32), ("k", 4)])
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# # #
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# scrambler
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self.submodules.scrambler = scrambler = _Scrambler(32)
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# insert K.29.7 as sync character
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# every sync_interval cycles
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count = Signal(max=sync_interval)
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="DISABLE"))
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self.comb += fsm.reset.eq(~self.enable)
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fsm.act("DISABLE",
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sink.connect(source, omit={"data"}),
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source.k.eq(0b0000),
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source.d.eq(sink.data),
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NextState("SYNC")
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)
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fsm.act("SYNC",
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scrambler.reset.eq(1),
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source.stb.eq(1),
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source.k[0].eq(1),
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source.d[:8].eq(K(29, 7)),
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NextValue(count, 0),
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If(source.ack,
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NextState("DATA")
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)
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)
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fsm.act("DATA",
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scrambler.i.eq(sink.data),
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sink.ack.eq(source.ack),
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source.stb.eq(1),
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source.d.eq(scrambler.o),
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If(source.stb & source.ack,
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scrambler.ce.eq(1),
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NextValue(count, count + 1),
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If(count == (sync_interval - 1),
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NextState("SYNC")
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)
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)
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)
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class Descrambler(Module):
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def __init__(self):
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self.enable = Signal()
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self.sink = sink = stream.Endpoint([("d", 32), ("k", 4)])
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self.source = source = stream.Endpoint([("data", 32)])
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# # #
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# descrambler
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self.submodules.descrambler = descrambler = _Scrambler(32)
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self.comb += descrambler.i.eq(sink.d)
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# detect K29.7 and synchronize descrambler
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="DISABLE"))
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self.comb += fsm.reset.eq(~self.enable)
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fsm.act("DISABLE",
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sink.connect(source, omit={"d", "k"}),
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source.data.eq(sink.d),
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NextState("SYNC_DATA")
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)
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fsm.act("SYNC_DATA",
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If((sink.k[0] == 1) &
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(sink.d[:8] == K(29,7)),
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sink.ack.eq(1),
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descrambler.reset.eq(1)
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).Else(
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sink.ack.eq(source.ack),
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source.stb.eq(sink.stb),
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source.data.eq(descrambler.o),
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If(source.stb & source.ack,
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descrambler.ce.eq(1)
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)
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)
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)
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