mirror of https://github.com/m-labs/artiq.git
Robert Jördens
307cd07b9d
tested/validated: * servo enable/disable * dds interface, timing, io_update, mask_nu * channel control (en_out, en_iir, profile) * profile configuration (coefficients, delays, offsets, channel) * adc timings and waveforms measured * asf state readback * adc readback individual changes below: suservo: correct rtio readback suservo: example, device_db [wip] suservo: change rtio channel layout suservo: mem ports in rio domain suservo: sck clocked from rio_phy suservo: cleanup, straighten out timing suservo: dds cs polarity suservo: simplify pipeline suservo: drop unused eem names suservo: decouple adc SR from IIR suservo: expand coredevice layer suservo: start the correct stage suservo: actually load ctrl suservo: refactor/tweak adc timing suservo: implement cpld and dds init |
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| .. | ||
| __init__.py | ||
| ad53xx_monitor.py | ||
| dds.py | ||
| sawg.py | ||
| servo.py | ||
| spi2.py | ||
| ttl_serdes_7series.py | ||
| ttl_serdes_generic.py | ||
| ttl_serdes_ultrascale.py | ||
| ttl_simple.py | ||
| wishbone.py | ||