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1620 Commits

Author SHA1 Message Date
whitequark b5cf1e395d runtime: avoid race condition when running kernel. 
Also, don't bother passing kernel name: entry point is already
recorded in DT_INIT when the kernel is linked.
 2015-08-07 08:51:33 +03:00
whitequark 1a969aa9e4 compiler.transforms.inferencer: accept and ignore @kernel decorator. 2015-08-07 07:54:35 +03:00
whitequark 7562d39750 compiler.module: split off inferencing from Module.__init__. 2015-08-06 08:25:53 +03:00
whitequark ca52b2fdd0 compiler.transforms.ARTIQIRGenerator: fix typo. 2015-08-06 08:25:53 +03:00
whitequark 98cd4288c1 artiq_personality: cast exception params so that %lld is always valid. 2015-08-06 08:25:53 +03:00
whitequark 722dfef97b artiq_personality: simplify. 2015-08-06 07:59:15 +03:00
whitequark 8d0222c297 Rename artiq_coreconfig → artiq_coretool; add log subcommand. 2015-08-02 16:40:43 +03:00
whitequark 62fdc75d2d Integrate libdyld and libunwind. 
It is currently possible to run the idle experiment, and it
can raise and catch exceptions, but exceptions are not yet
propagated across RPC boundaries.
 2015-08-02 15:43:03 +03:00
whitequark 6db93b34e8 artiq_personality: port to device. 2015-08-02 06:34:11 +03:00
whitequark aae2923c4c runtime: add lognonl{,_va} functions. 
The kernels have print(), which prints aggregates (such as
arrays) piece-by-piece, and newlines would interfere.
 2015-08-02 06:33:12 +03:00
whitequark cd294e2986 artiq_personality: avoid unaligned loads. 2015-08-02 06:28:58 +03:00
whitequark 697b78ddf2 Rename {kserver → net_server}.{c,h}. 2015-07-30 13:45:57 +03:00
whitequark e8943a008c Rename compiler/{targets/__init__.py → targets.py}. 2015-07-30 10:35:04 +03:00
whitequark 1e3911ed39 Use try..finally in compiler.targets.Target.link. 2015-07-30 10:33:54 +03:00
whitequark b0185f3917 Add profiling to the performance testbench. 2015-07-29 22:23:22 +03:00
whitequark d7f9af4bb5 Fix accidentally quadratic code in compiler.ir.Function._add_name. 2015-07-29 21:36:31 +03:00
whitequark 6d8d0ff3f5 Update performance testbench to include time spent in ARTIQ. 2015-07-29 21:28:07 +03:00
whitequark 3b5d3e2b1a Add a performance measurement testbench. 2015-07-29 21:17:52 +03:00
whitequark e8c107925c Implement shared object linking. 2015-07-29 20:35:16 +03:00
whitequark 2cd25f85bf Rename artiq.compiler.testbench.{module → signature}. 2015-07-29 14:32:34 +03:00
whitequark 3378dd57b8 Fold llvmlite patches into m-labs/llvmlite repository. 2015-07-29 13:54:00 +03:00
whitequark fd46d8b11e Merge branch 'master' into new-py2llvm 2015-07-29 12:52:19 +03:00
whitequark c40ae9dbd3 MiSoC is not built with -fPIC anymore, remove support code for that. 2015-07-29 12:40:46 +03:00
Robert Jördens ebbbdcf194 examples/tdr: cleanup 2015-07-28 23:30:26 -06:00
Robert Jördens 278570faf6 examples: add TDR toy example 2015-07-28 21:36:10 -06:00
Sebastien Bourdeauducq 90368415a6 ttl: remove timestamp function 
The general idea is that functions that work with absolute timestamps exist only in machine units versions, to help prevent floating point losses of precision. Time differences should be computed in machine units and then converted, e.g. mu_to_seconds(t2-t1).

This function would have had problems after ~50 days of running the device.
 2015-07-29 11:11:16 +08:00
Robert Jördens 2640a57af3 test/coredevice: let output() settle longer 2015-07-28 16:20:05 -06:00
Robert Jördens 5f5227f01f ttl: add timestamp() 2015-07-28 16:20:05 -06:00
Robert Jördens e95b66f114 ttl: remove spurious _mu 2015-07-28 16:20:05 -06:00
whitequark b179430f6b Specify correct llvmlite branch in installation instructions. 2015-07-28 23:43:07 +03:00
Robert Jördens 67715f0d2e pipistrello: only put serdes on the lower ttls 
this setup is getting a bit power hungry.

pmt0, 1 (rtio channels 0, 1): 4x in and out
ttl0, 1 (rtio channels 2, 3): 4x out
ttl2 (rtio channel 4): 8x out
 2015-07-28 12:54:31 -06:00
Robert Jördens fb339d294e serdes_s6: no need to reset 2015-07-28 12:54:31 -06:00
Robert Jördens 9dfbf07743 pipistrello: use 4x serdes for rtio ttl 
pipistrello: do not wait for lock on startup

LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
 2015-07-28 12:54:27 -06:00
Sebastien Bourdeauducq 8e391e2661 kc705: generate 10MHz clock on GPIO SMA 
For SynthNV and input tests.
 2015-07-28 18:56:47 +08:00
Robert Jördens 1809a70f5c Revert "pipistrello: use 4x serdes for rtio ttl" 
This reverts commit 8e92cc91f5.

Broken. Will revisit.
 2015-07-27 23:39:35 -06:00
Robert Jördens f0a7078336 Revert "rtiocrg.c: pipistrello also has pll_reset" 
This reverts commit bdee914828.
 2015-07-27 22:18:45 -06:00
Robert Jördens bdee914828 rtiocrg.c: pipistrello also has pll_reset 2015-07-27 22:14:42 -06:00
Robert Jördens e95b06e96d pipistrello: tie unused dds.p low 2015-07-27 21:48:56 -06:00
Robert Jördens 8e92cc91f5 pipistrello: use 4x serdes for rtio ttl 2015-07-27 21:29:50 -06:00
Robert Jördens 9ac5bc52d4 rtio: add spartan6 serdes, 4x and 8x 2015-07-27 21:01:15 -06:00
Sebastien Bourdeauducq ae3a52c49c runtime: fix KERNELCPU_PAYLOAD_ADDRESS 2015-07-28 02:12:14 +08:00
whitequark eec4a2d2d2 Update buildsystem to track -fPIC and ranlib removal in MiSoC. 2015-07-27 21:10:46 +03:00
Sebastien Bourdeauducq 0cd74533ca runtime: more explicit message about startup clock failure 2015-07-28 00:38:38 +08:00
Sebastien Bourdeauducq 228f7c3d61 manual: update xc3sprog download 2015-07-28 00:38:20 +08:00
Sebastien Bourdeauducq 7feaca7c7c runtime: allow selecting external clock at startup 2015-07-28 00:19:07 +08:00
Sebastien Bourdeauducq 09d837e4ba runtime: monitor RTIO clock status 2015-07-28 00:05:24 +08:00
Sebastien Bourdeauducq 299bc1cb7e kc705: output divided-by-2 RTIO clock 2015-07-27 20:46:44 +08:00
Sebastien Bourdeauducq 256e99f0d7 kc705: crg cleanup 2015-07-27 20:31:37 +08:00
Sebastien Bourdeauducq 2a95e866aa kc705: use 8X SERDES RTIO PHY 2015-07-27 20:12:17 +08:00
Sebastien Bourdeauducq fe57308e71 runtime: support for RTIO PLL 2015-07-27 20:11:31 +08:00