14 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	8f608fa2fa	examples/sines_urukul_sayma: adapt for sayma v2, use 1 DAC only	2020-04-05 16:51:40 +08:00
Sebastien Bourdeauducq	82cdb7f933	typo	2020-01-21 10:07:13 +08:00
Sebastien Bourdeauducq	8f9948a1ff	kasli_sawgmaster: add basemod programming example	2020-01-20 20:14:24 +08:00
Sebastien Bourdeauducq	106d25b32a	kasli_sawgmaster: fix drtio_is_up	2019-12-21 14:17:52 +08:00
Sebastien Bourdeauducq	2e8decbce3	kasli_sawgmaster: generate a HMC830 clock with Urukul	2019-01-29 15:06:45 +08:00
Sebastien Bourdeauducq	d1ef036948	kasli_sawgmaster: initialize SAWG phase according to RTIO TSC	2019-01-27 09:49:31 +08:00
Sebastien Bourdeauducq	a92cc91dcb	kasli_sawgmaster: correctly tune DDS and SAWG	2019-01-24 19:37:14 +08:00
David Nadlinger	101ed5d534	examples: Fix DRTIO destination indices (#1231) ... Using the default routing table, links numbers and destinations are offset by 1, as destination 0 is local RTIO.	2019-01-09 11:40:15 +08:00
Sebastien Bourdeauducq	c8cd830118	drtio: implement get_rtio_destination_status for kernels	2018-09-15 19:11:22 +08:00
Sebastien Bourdeauducq	8b8e1844f0	kasli_sawgmaster: roughly match Urukul and Sayma amplitudes	2018-08-07 20:07:21 +08:00
Sebastien Bourdeauducq	8aa88cfe70	kasli_sawgmaster: add Urukul-Sayma example	2018-08-07 19:29:28 +08:00
Sebastien Bourdeauducq	65f198bdee	kasli: use tester EEMs for DRTIO, add Urukul-Sayma sync example	2018-08-06 16:53:13 +08:00
Sebastien Bourdeauducq	04d6ff45c8	kasli_sawgmaster: reset SAWGs ... Most importantly this resets the phase accumulators.	2018-06-28 17:01:48 +08:00
Sebastien Bourdeauducq	51a5d8dff9	examples: add Kasli SAWG master	2018-06-22 18:57:49 +08:00