mirror of https://github.com/m-labs/artiq.git
examples: Fix DRTIO destination indices (#1231)
Using the default routing table, links numbers and destinations are offset by 1, as destination 0 is local RTIO.
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@ -6,12 +6,18 @@ class Sines2Sayma(EnvExperiment):
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self.setattr_device("core")
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self.sawgs = [self.get_device("sawg"+str(i)) for i in range(16)]
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@kernel
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def drtio_is_up(self):
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for i in range(3):
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if not self.core.get_rtio_destination_status(i):
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return False
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return True
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@kernel
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def run(self):
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while True:
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print("waiting for DRTIO ready...")
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while not (self.core.get_rtio_destination_status(0) and
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self.core.get_rtio_destination_status(1)):
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while not self.drtio_is_up():
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pass
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print("OK")
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@ -27,5 +33,5 @@ class Sines2Sayma(EnvExperiment):
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# Do not use a sub-multiple of oscilloscope sample rates.
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sawg.frequency0.set(9*MHz)
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while self.core.get_rtio_destination_status(0) and self.core.get_rtio_destination_status(1):
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while self.drtio_is_up():
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pass
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@ -8,6 +8,13 @@ class SinesUrukulSayma(EnvExperiment):
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self.urukul_chs = [self.get_device("urukul0_ch" + str(i)) for i in range(4)]
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self.sawgs = [self.get_device("sawg"+str(i)) for i in range(8)]
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@kernel
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def drtio_is_up(self):
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for i in range(2):
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if not self.core.get_rtio_destination_status(i):
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return False
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return True
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@kernel
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def run(self):
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# Note: when testing sync, do not reboot Urukul, as it is not
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@ -23,7 +30,7 @@ class SinesUrukulSayma(EnvExperiment):
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while True:
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print("waiting for DRTIO ready...")
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while not self.core.get_rtio_destination_status(0):
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while not self.drtio_is_up():
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pass
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print("OK")
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@ -38,5 +45,5 @@ class SinesUrukulSayma(EnvExperiment):
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sawg.amplitude1.set(.4)
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sawg.frequency0.set(9*MHz)
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while self.core.get_rtio_destination_status(0):
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while self.drtio_is_up():
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pass
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@ -10,8 +10,9 @@ class SAWGTestDRTIO(EnvExperiment):
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@kernel
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def run(self):
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core_log("waiting for DRTIO ready...")
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while not self.core.get_rtio_destination_status(0):
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pass
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for i in range(3):
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while not self.core.get_rtio_destination_status(i):
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pass
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core_log("OK")
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self.core.reset()
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