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601f593ac4
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targets/kc705: do not depend on particular Migen generated signal names
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2015-04-11 21:46:57 +08:00 |
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Florent Kermarrec
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bdd02a064e
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targets/artiq_kc705: add false path between rsys_clk and rio_clk (reduce P&R on AMP from 40 minutes to 5 minutes :)
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2015-04-11 21:32:46 +08:00 |
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Florent Kermarrec
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24b2bd7b6f
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soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds
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2015-04-11 21:32:11 +08:00 |
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fb75bd246e
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targets/kc705: make AMP the default
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2015-04-11 17:16:25 +08:00 |
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b492aad1c4
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targets/kc705: enable Ethernet core
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2015-04-10 13:15:32 +08:00 |
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44304a33b2
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soc,runtime: define RTIO FUD channel number in targets
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2015-04-09 00:35:11 +08:00 |
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7e591bb1c7
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targets: use _Peripherals/UP/AMP class names, share QC1 IO defs
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2015-04-07 00:07:53 +08:00 |
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277e038569
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targets/kc705: add LED on RTIO
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2015-04-04 22:07:23 +08:00 |
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5f7161a7de
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kc705: 16 TTLs
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2015-04-03 15:57:25 +08:00 |
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Florent Kermarrec
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2995f0a705
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remove use of _r prefix on CSRs
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2015-04-02 18:30:44 +08:00 |
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88a1707ef9
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soc: use new location of gpio module
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2015-04-02 17:19:00 +08:00 |
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5fd7f68f48
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targets/kc705: dual-CPU design
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2015-04-02 16:53:57 +08:00 |
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28bce9ee40
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artiqlib -> artiq.gateware
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2015-03-08 11:00:24 +01:00 |
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4e5320be28
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Merge branch 'master' of https://github.com/m-labs/artiq
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2015-02-28 07:34:38 -07:00 |
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Florent Kermarrec
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9cf8db2f14
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adapt code to MiSoC's changes
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2015-02-28 07:34:11 -07:00 |
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Joe Britton
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0127de9bb5
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soc: add_cpu_csr_region -> add_csr_region
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2015-02-27 15:02:28 -07:00 |
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da917f768e
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initial kc705 support
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2015-02-26 21:50:52 -07:00 |
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