2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-21 09:26:29 +08:00
Commit Graph

3803 Commits

Author SHA1 Message Date
577754c38f pdq2: fix argparser 2015-03-19 22:26:12 -06:00
222d0a9d37 pdq2_controller: add dump option 2015-03-19 21:38:46 -06:00
5ab3290ed4 pdq2: add refactored client code 2015-03-19 20:34:29 -06:00
fae7246f30 pdq2: merge from main pdq2 repo 2015-03-19 14:34:37 -06:00
fdca0a71ff add ARTIQMidiSoC based on pipistrello 2015-03-19 11:37:15 -06:00
2257cfa952 wavesynth/compute_samples/: demonstrate dds clear 2015-03-15 18:13:47 +01:00
40bd101de0 wavesynth/compute_samples/SplinePhase: fix reduction 2015-03-15 18:13:09 +01:00
1d0fde7f13 wavesynth: program decoding 2015-03-15 18:05:03 +01:00
327448977c wavesynth/compute_samples: use set_coefficients 2015-03-15 16:48:24 +01:00
0d8260af6e wavesynth: basic sample computation 2015-03-15 16:30:07 +01:00
2b3641ac0a db,worker: fix realtime result initialization 2015-03-13 15:12:55 +01:00
7a1d60ee15 coredevice,runtime,language: add parameters to runtime exceptions, include information with RTIO errors 2015-03-13 14:55:18 +01:00
84732a469d coredevice/gpio: fix indentation 2015-03-13 14:31:50 +01:00
330e7e1b18 doc/manual: add note about avoiding __del__ 2015-03-12 15:15:56 +01:00
0416da8634 runtime/test: implement ttlout, clksel and dds functions 2015-03-12 13:14:06 +01:00
3122623c6f rtio: make 63-bit timestamp counter the default [soc] 2015-03-12 13:13:35 +01:00
d38014b07d soc/runtime: import DDS/TTL tester (functions not accessible yet) 2015-03-11 22:02:19 +01:00
f158711f7e test/worker: test watchdog in build() 2015-03-11 19:07:04 +01:00
43a05c783d worker: split write_results action 2015-03-11 19:06:46 +01:00
4ba54ac929 test: do not close/recreate the asyncio event loop (WA for asyncio bugs when multiple tests are run) 2015-03-11 19:05:01 +01:00
e037b930d8 test: add worker unittest 2015-03-11 18:26:04 +01:00
5ca4821a29 ctlmgr: use workaround for asyncio.wait_for(process.wait()... Python bug 2015-03-11 16:48:16 +01:00
d5795fd619 master: watchdog support
Introduces a watchdog context manager to use in the experiment code that
terminates the process with an error if it times out. The syntax is:

with self.scheduler.watchdog(20*s):
   ...

Watchdogs timers are implemented by the master process (and the worker
communicates the necessary information about them) so that they can be
enforced even if the worker crashes. They can be nested arbitrarily.
During yields, all watchdog timers for the yielding worker are
suspended [TODO]. Setting up watchdogs is not supported in kernels,
however, a kernel can be called within watchdog contexts (and terminating
the worker will terminate the kernel [TODO]).

It is possible to implement a heartbeat mechanism using a watchdog, e.g.:

for i in range(...):
    with self.scheduler.watchdog(...):
        ....

Crashes/freezes within the iterator or the loop management would not be
detected, but they should be rare enough.
2015-03-11 16:43:14 +01:00
f2134fa4b2 master,worker: split prepare/run/analyze 2015-03-09 23:34:09 +01:00
4c280d5fcc master: use a new worker process for each experiment 2015-03-09 16:22:41 +01:00
ec1d082730 remove timeout from run_params (to be replaced by a better mechanism) 2015-03-09 10:51:32 +01:00
d95a9cac9a move realtime result registration into dbh, simplify syntax 2015-03-08 17:27:27 +01:00
f2e3dfb848 Experiment base class, replace __artiq_unit__ with docstring 2015-03-08 15:55:30 +01:00
407477bc5a test: add ARTIQ_NO_PERIPHERALS environment variable to disable tests requiring non-core devices 2015-03-08 11:40:50 +01:00
0f007cb1a7 language/db: remove implicit_core 2015-03-08 11:37:53 +01:00
ac697e3248 test/thorlabs_tcube: fix default serial port 2015-03-08 11:37:24 +01:00
28bce9ee40 artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
9fad01d967 test/thorlabs_tcube: fix test discovery and style 2015-03-04 23:53:49 +00:00
Yann Sionneau
c2831db253 thorlabs_tcube: add realistic values for status bits and dc status in driver sim 2015-03-04 23:45:22 +00:00
Yann Sionneau
5091098eb0 thorlabs_tcube: driver PEP8 fix 2015-03-04 23:45:21 +00:00
Yann Sionneau
bc19d6f7a8 thorlabs_tcube: add unit tests 2015-03-04 23:45:21 +00:00
Yann Sionneau
5b8691f7f5 thorlabs_tcube: fix driver spelling issues 2015-03-04 23:45:21 +00:00
Yann Sionneau
14c759ff89 add Thorlabs T-Cube NDSP 2015-03-04 14:30:49 +00:00
6062b42117 doc: update overview slides 2015-03-03 22:45:14 +00:00
15d09c0b94 runtime: use new uart tuning word function 2015-03-02 23:36:05 +00:00
4e5320be28 Merge branch 'master' of https://github.com/m-labs/artiq 2015-02-28 07:34:38 -07:00
Florent Kermarrec
9cf8db2f14 adapt code to MiSoC's changes 2015-02-28 07:34:11 -07:00
7028d85255 targets/ppro: disable L2 2015-02-27 18:02:21 -07:00
Joe Britton
0127de9bb5 soc: add_cpu_csr_region -> add_csr_region 2015-02-27 15:02:28 -07:00
f307897bec units: fix strip_unit 2015-02-27 10:43:03 -07:00
0abd41a04a pc_rpc: trace support in server 2015-02-27 00:17:11 -07:00
3e46a36a4d lda: do not print attenuation value in simulation 2015-02-27 00:16:56 -07:00
61f33a9a04 soc/ad9858: do not put code in __init__.py 2015-02-26 23:31:43 -07:00
ee9d616733 language/units: add strip_unit function 2015-02-26 23:31:07 -07:00
14e481d154 benchmarks: fix imports 2015-02-26 23:21:24 -07:00