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Revert "phaser: cap phy data width to 64 temporarily" 

This reverts commit 342b9e977e.
This commit is contained in:
Robert Jördens 2016-11-18 17:08:44 +01:00
parent 641f07119f
commit bcde26f990
1 changed files with 1 additions and 2 deletions
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artiq/gateware/rtio/phy/sawg.py
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@ -16,8 +16,7 @@ class Channel(_ChannelPHY):
_ChannelPHY.__init__(self, *args, **kwargs) _ChannelPHY.__init__(self, *args, **kwargs)
self.phys = [] self.phys = []
for i in self.i: for i in self.i:
rl = rtlink.Interface(rtlink.OInterface( rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
min(64, len(i.payload)))) # FIXME
self.comb += [ self.comb += [
i.stb.eq(rl.o.stb), i.stb.eq(rl.o.stb),
rl.o.busy.eq(~i.ack), rl.o.busy.eq(~i.ack),