From bcde26f99034edebb8d73bf0eaad0ff5a287485b Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Fri, 18 Nov 2016 17:08:44 +0100
Subject: [PATCH] Revert "phaser: cap phy data width to 64 temporarily"

This reverts commit 342b9e977ee594d49cdb3c233c89bc796a391cc4.
---
 artiq/gateware/rtio/phy/sawg.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/artiq/gateware/rtio/phy/sawg.py b/artiq/gateware/rtio/phy/sawg.py
index 5b15806e6..84094f5a2 100644
--- a/artiq/gateware/rtio/phy/sawg.py
+++ b/artiq/gateware/rtio/phy/sawg.py
@@ -16,8 +16,7 @@ class Channel(_ChannelPHY):
         _ChannelPHY.__init__(self, *args, **kwargs)
         self.phys = []
         for i in self.i:
-            rl = rtlink.Interface(rtlink.OInterface(
-                min(64, len(i.payload))))  # FIXME
+            rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
             self.comb += [
                 i.stb.eq(rl.o.stb),
                 rl.o.busy.eq(~i.ack),