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dma: report last write to FIFO

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occheung 2025-01-10 16:09:39 +08:00
parent 41933b8849
commit 585b9875eb
1 changed files with 1 additions and 0 deletions
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artiq/gateware/rtio/dma.py
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@ -66,6 +66,7 @@ class WishboneReader(Module):
self.source.stb.eq(bus.ack),
self.source.data.eq(convert_signal(bus.dat_r, cpu_dw//8)),
self.source.last.eq(self.sink.eop | last),
self.source.eop.eq(self.sink.eop),
]