From 585b9875eb8f659aa75c7a04cfb6310518090f94 Mon Sep 17 00:00:00 2001 From: occheung Date: Fri, 10 Jan 2025 16:09:39 +0800 Subject: [PATCH] dma: report last write to FIFO --- artiq/gateware/rtio/dma.py | 1 + 1 file changed, 1 insertion(+) diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py index f187633b0..2c9895152 100644 --- a/artiq/gateware/rtio/dma.py +++ b/artiq/gateware/rtio/dma.py @@ -66,6 +66,7 @@ class WishboneReader(Module): self.source.stb.eq(bus.ack), self.source.data.eq(convert_signal(bus.dat_r, cpu_dw//8)), + self.source.last.eq(self.sink.eop | last), self.source.eop.eq(self.sink.eop), ]