diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py
index f187633b0..2c9895152 100644
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@@ -66,6 +66,7 @@ class WishboneReader(Module):
             self.source.stb.eq(bus.ack),
 
             self.source.data.eq(convert_signal(bus.dat_r, cpu_dw//8)),
+            self.source.last.eq(self.sink.eop | last),
             self.source.eop.eq(self.sink.eop),
         ]