M-Labs/artiq-zynq
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117_rtio_channels #147

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sb10q merged 10 commits from mwojcik/artiq-zynq:117_rtio_channels into master 2021-10-13 17:20:25 +08:00
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1 changed files with 19 additions and 29 deletions
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src/gateware/zc706.py
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@ -99,6 +99,25 @@ pmod1_33 = [
("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")), ("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")),
] ]
_ams101_dac = [
("ams101_dac", 0,
Subsignal("ldac", Pins("XADC:GPIO0")),
Subsignal("clk", Pins("XADC:GPIO1")),
Subsignal("mosi", Pins("XADC:GPIO2")),
Subsignal("cs_n", Pins("XADC:GPIO3")),
IOStandard("LVTTL")
)
]
_sdcard_spi_33 = [
("sdcard_spi_33", 0,
Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")),
Subsignal("clk", Pins("B20")),
Subsignal("mosi", Pins("J18")),
Subsignal("cs_n", Pins("H18")),
IOStandard("LVCMOS33")
)
]
def prepare_zc706_platform(platform): def prepare_zc706_platform(platform):
platform.toolchain.bitstream_commands.extend([ platform.toolchain.bitstream_commands.extend([
@ -437,35 +456,7 @@ class _SatelliteBase(SoCCore):
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table") self.csr_devices.append("routing_table")
# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
# This also changes the I/O standard for some on-board LEDs.
leds_fmc33 = [
("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
]
# todo: verify if gpio pins/expansion port on xadc is the same as on kc705
_ams101_dac = [
("ams101_dac", 0,
Subsignal("ldac", Pins("XADC:GPIO0")),
Subsignal("clk", Pins("XADC:GPIO1")),
Subsignal("mosi", Pins("XADC:GPIO2")),
Subsignal("cs_n", Pins("XADC:GPIO3")),
IOStandard("LVTTL")
)
]
_sdcard_spi_33 = [
("sdcard_spi_33", 0,
Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")),
Subsignal("clk", Pins("B20")),
Subsignal("mosi", Pins("J18")),
Subsignal("cs_n", Pins("H18")),
IOStandard("LVCMOS33")
)
]
class _NIST_CLOCK_RTIO: class _NIST_CLOCK_RTIO:
""" """
@ -501,7 +492,6 @@ class _NIST_CLOCK_RTIO:
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# could check the LED #
phy = ttl_simple.Output(platform.request("user_led_33", 2)) phy = ttl_simple.Output(platform.request("user_led_33", 2))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))