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@ -88,6 +88,36 @@ si5324_fmc33 = [ |
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), |
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] |
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pmod1_33 = [ |
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("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")), |
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("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")), |
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("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")), |
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("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")), |
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("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")), |
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("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")), |
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("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")), |
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("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")), |
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] |
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_ams101_dac = [ |
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("ams101_dac", 0, |
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Subsignal("ldac", Pins("XADC:GPIO0")), |
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Subsignal("clk", Pins("XADC:GPIO1")), |
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Subsignal("mosi", Pins("XADC:GPIO2")), |
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Subsignal("cs_n", Pins("XADC:GPIO3")), |
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IOStandard("LVTTL") |
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) |
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] |
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_sdcard_spi_33 = [ |
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("sdcard_spi_33", 0, |
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Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")), |
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Subsignal("clk", Pins("B20")), |
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Subsignal("mosi", Pins("J18")), |
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Subsignal("cs_n", Pins("H18")), |
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IOStandard("LVCMOS33") |
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) |
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] |
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def prepare_zc706_platform(platform): |
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platform.toolchain.bitstream_commands.extend([ |
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@ -427,6 +457,7 @@ class _SatelliteBase(SoCCore): |
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self.csr_devices.append("routing_table") |
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class _NIST_CLOCK_RTIO: |
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""" |
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NIST clock hardware, with old backplane and 11 DDS channels |
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@ -435,14 +466,12 @@ class _NIST_CLOCK_RTIO: |
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platform = self.platform |
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platform.add_extension(nist_clock.fmc_adapter_io) |
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platform.add_extension(leds_fmc33) |
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platform.add_extension(pmod1_33) |
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platform.add_extension(_ams101_dac) |
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platform.add_extension(_sdcard_spi_33) |
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rtio_channels = [] |
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for i in range(4): |
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phy = ttl_simple.Output(platform.request("user_led_33", i)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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for i in range(16): |
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if i % 4 == 3: |
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) |
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@ -458,16 +487,40 @@ class _NIST_CLOCK_RTIO: |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) |
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# no SMA GPIO, replaced with PMOD1_0 |
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phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) |
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phy = ttl_simple.Output(platform.request("user_led_33", 0)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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ams101_dac = self.platform.request("ams101_dac", 0) |
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phy = ttl_simple.Output(ams101_dac.ldac) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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phy = ttl_simple.ClockGen(platform.request("la32_p")) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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phy = spi2.SPIMaster(ams101_dac) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy( |
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phy, ififo_depth=4)) |
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for i in range(3): |
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phy = spi2.SPIMaster(self.platform.request("spi", i)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy( |
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phy, ififo_depth=128)) |
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phy = spi2.SPIMaster(platform.request("sdcard_spi_33")) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy( |
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phy, ififo_depth=4)) |
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) |
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@ -487,26 +540,41 @@ class _NIST_QC2_RTIO: |
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platform = self.platform |
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platform.add_extension(nist_qc2.fmc_adapter_io) |
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platform.add_extension(leds_fmc33) |
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platform.add_extension(_ams101_dac) |
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rtio_channels = [] |
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for i in range(4): |
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phy = ttl_simple.Output(platform.request("user_led_33", i)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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# All TTL channels are In+Out capable |
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for i in range(40): |
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phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) |
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# no SMA GPIO, replaced with PMOD1_0 |
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phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) |
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phy = ttl_simple.Output(platform.request("user_led_33", 0)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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ams101_dac = self.platform.request("ams101_dac", 0) |
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phy = ttl_simple.Output(ams101_dac.ldac) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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# CLK0, CLK1 are for clock generators, on backplane SMP connectors |
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for i in range(2): |
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phy = ttl_simple.ClockGen( |
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platform.request("clkout", i)) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy(phy)) |
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phy = spi2.SPIMaster(ams101_dac) |
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self.submodules += phy |
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rtio_channels.append(rtio.Channel.from_phy( |
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phy, ififo_depth=4)) |
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for i in range(4): |
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phy = spi2.SPIMaster(self.platform.request("spi", i)) |
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