From ac29cd30e504a2485d6c4234f5a3019ff42bbf6a Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 5 Oct 2021 09:53:07 +0200 Subject: [PATCH 1/8] added scripts from drtio port --- default.nix | 28 +++++++++++++++---- kasli-soc-master.json | 60 ++++++++++++++++++++++++++++++++++++++++ kasli-soc-satellite.json | 60 ++++++++++++++++++++++++++++++++++++++++ local_run.sh | 9 ++++-- remote_run.sh | 9 ++++-- src/Cargo.toml | 2 ++ src/Makefile | 18 ++++++++++-- 7 files changed, 171 insertions(+), 15 deletions(-) create mode 100644 kasli-soc-master.json create mode 100644 kasli-soc-satellite.json diff --git a/default.nix b/default.nix index a9b7f19..cb28ac1 100644 --- a/default.nix +++ b/default.nix @@ -8,12 +8,14 @@ let vivado = import { inherit pkgs; }; # FSBL configuration supplied by Vivado 2020.1 for these boards: fsblTargets = ["zc702" "zc706" "zed"]; + sat_variants = ["satellite" "acpki_satellite" "nist_clock_satellite" "nist_qc2_satellite"]; build = { target, variant, json ? null }: let szl = (import zynq-rs)."${target}-szl"; fsbl = import "${zynq-rs}/nix/fsbl.nix" { inherit pkgs; board = target; }; + fwtype = if builtins.elem variant sat_variants then "satman" else "runtime"; firmware = rustPlatform.buildRustPackage rec { # note: due to fetchCargoTarball, cargoSha256 depends on package name @@ -33,15 +35,15 @@ let export XARGO_RUST_SRC="${rustPlatform.rust.rustc}/lib/rustlib/src/rust/library" export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_9.clang-unwrapped.lib}/lib/clang/9.0.1/include" export CARGO_HOME=$(mktemp -d cargo-home.XXX) - make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" + make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype} ''; installPhase = '' mkdir -p $out $out/nix-support - cp ../build/runtime.bin $out/runtime.bin - cp ../build/firmware/armv7-none-eabihf/release/runtime $out/runtime.elf - echo file binary-dist $out/runtime.bin >> $out/nix-support/hydra-build-products - echo file binary-dist $out/runtime.elf >> $out/nix-support/hydra-build-products + cp ../build/${fwtype}.bin $out/${fwtype}.bin + cp ../build/firmware/armv7-none-eabihf/release/${fwtype} $out/${fwtype}.elf + echo file binary-dist $out/${fwtype}.bin >> $out/nix-support/hydra-build-products + echo file binary-dist $out/${fwtype}.elf >> $out/nix-support/hydra-build-products ''; doCheck = false; @@ -66,7 +68,7 @@ let '' mkdir $out ln -s ${szl}/szl.elf $out - ln -s ${firmware}/runtime.bin $out + ln -s ${firmware}/${fwtype}.bin $out ln -s ${gateware}/top.bit $out ''; sd = pkgs.runCommand "${target}-${variant}-sd" @@ -132,11 +134,25 @@ let in ( (build { target = "zc706"; variant = "simple"; }) // + (build { target = "zc706"; variant = "master"; }) // + (build { target = "zc706"; variant = "satellite"; }) // (build { target = "zc706"; variant = "nist_clock"; }) // + (build { target = "zc706"; variant = "nist_clock_master"; }) // + (build { target = "zc706"; variant = "nist_clock_satellite"; }) // (build { target = "zc706"; variant = "nist_qc2"; }) // + (build { target = "zc706"; variant = "nist_qc2_master"; }) // + (build { target = "zc706"; variant = "nist_qc2_satellite"; }) // (build { target = "zc706"; variant = "acpki_simple"; }) // + (build { target = "zc706"; variant = "acpki_master"; }) // + (build { target = "zc706"; variant = "acpki_satellite"; }) // (build { target = "zc706"; variant = "acpki_nist_clock"; }) // + (build { target = "zc706"; variant = "acpki_nist_clock_master"; }) // + (build { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) // (build { target = "zc706"; variant = "acpki_nist_qc2"; }) // + (build { target = "zc706"; variant = "acpki_nist_qc2_master"; }) // + (build { target = "zc706"; variant = "acpki_nist_qc2_satellite"; }) // (build { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) // + (build { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) // + (build { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) // { inherit zynq-rs; } ) diff --git a/kasli-soc-master.json b/kasli-soc-master.json new file mode 100644 index 0000000..1de434f --- /dev/null +++ b/kasli-soc-master.json @@ -0,0 +1,60 @@ +{ + "target": "kasli_soc", + "variant": "master", + "hw_rev": "v1.0", + "base": "master", + "peripherals": [ + { + "type": "grabber", + "ports": [0] + }, + { + "type": "dio", + "ports": [1], + "bank_direction_low": "input", + "bank_direction_high": "output" + }, + { + "type": "dio", + "ports": [2], + "bank_direction_low": "output", + "bank_direction_high": "output" + }, + { + "type": "urukul", + "dds": "ad9910", + "ports": [3, 4], + "clk_sel": 2 + }, + { + "type": "zotino", + "ports": [5] + }, + { + "type": "sampler", + "ports": [6, 7] + }, + { + "type": "mirny", + "ports": [8], + "clk_sel": 1, + "refclk": 125e6 + }, + { + "type": "fastino", + "ports": [9] + }, + { + "type": "dio", + "ports": [10], + "bank_direction_low": "input", + "bank_direction_high": "input" + }, + { + "type": "dio", + "ports": [11], + "bank_direction_low": "output", + "bank_direction_high": "input" + } + ] +} diff --git a/kasli-soc-satellite.json b/kasli-soc-satellite.json new file mode 100644 index 0000000..7eafabf --- /dev/null +++ b/kasli-soc-satellite.json @@ -0,0 +1,60 @@ +{ + "target": "kasli_soc", + "variant": "satellite", + "hw_rev": "v1.0", + "base": "satellite", + "peripherals": [ + { + "type": "grabber", + "ports": [0] + }, + { + "type": "dio", + "ports": [1], + "bank_direction_low": "input", + "bank_direction_high": "output" + }, + { + "type": "dio", + "ports": [2], + "bank_direction_low": "output", + "bank_direction_high": "output" + }, + { + "type": "urukul", + "dds": "ad9910", + "ports": [3, 4], + "clk_sel": 2 + }, + { + "type": "zotino", + "ports": [5] + }, + { + "type": "sampler", + "ports": [6, 7] + }, + { + "type": "mirny", + "ports": [8], + "clk_sel": 1, + "refclk": 125e6 + }, + { + "type": "fastino", + "ports": [9] + }, + { + "type": "dio", + "ports": [10], + "bank_direction_low": "input", + "bank_direction_high": "input" + }, + { + "type": "dio", + "ports": [11], + "bank_direction_low": "output", + "bank_direction_high": "input" + } + ] +} diff --git a/local_run.sh b/local_run.sh index a423d41..f72d223 100755 --- a/local_run.sh +++ b/local_run.sh @@ -14,8 +14,9 @@ fi impure=0 load_bitstream=1 board_type="kasli_soc" +fw_type="runtime" -while getopts "ilb:t:" opt; do +while getopts "ilb:t:f:" opt; do case "$opt" in \?) exit 1 ;; @@ -27,6 +28,8 @@ while getopts "ilb:t:" opt; do ;; t) board_type=$OPTARG ;; + f) fw_type=$OPTARG + ;; esac done @@ -49,10 +52,10 @@ if [ $impure -eq 1 ]; then if [ $load_bitstream -eq 1 ]; then load_bitstream_cmd="-g $build_dir/gateware/top.bit" fi - artiq_netboot $load_bitstream_cmd -f $build_dir/runtime.bin -b $board_host + artiq_netboot $load_bitstream_cmd -f $build_dir/$fwtype.bin -b $board_host else if [ $load_bitstream -eq 1 ]; then load_bitstream_cmd="-g $result_dir/top.bit" fi - artiq_netboot $load_bitstream_cmd -f $result_dir/runtime.bin -b $board_host + artiq_netboot $load_bitstream_cmd -f $result_dir/$fwtype.bin -b $board_host fi diff --git a/remote_run.sh b/remote_run.sh index fe3e479..9a22997 100755 --- a/remote_run.sh +++ b/remote_run.sh @@ -20,8 +20,9 @@ impure_dir="build" sshopts="" load_bitstream=1 board_host="192.168.1.52" +fw_type="runtime" -while getopts "h:id:o:l" opt; do +while getopts "h:id:o:lt:" opt; do case "$opt" in \?) exit 1 ;; @@ -38,6 +39,8 @@ while getopts "h:id:o:l" opt; do ;; b) board_host=$OPTARG ;; + t) fw_type=$OPTARG + ;; esac done @@ -53,12 +56,12 @@ if [ $impure -eq 1 ]; then if [ $load_bitstream -eq 1 ]; then load_bitstream_cmd="-g build/gateware/top.bit" fi - firmware="build/runtime.bin" + firmware="build/$fw_type.bin" else if [ $load_bitstream -eq 1 ]; then load_bitstream_cmd="-g $pure_dir/top.bit" fi - firmware="$pure_dir/runtime.bin" + firmware="$pure_dir/$fw_type.bin" fi echo "Programming board..." ssh $sshopts $target_host "cd $target_folder; openocd -f zc706.cfg -c'load_image szl.elf; resume 0; exit'" diff --git a/src/Cargo.toml b/src/Cargo.toml index 89b241e..f8473e4 100644 --- a/src/Cargo.toml +++ b/src/Cargo.toml @@ -3,8 +3,10 @@ members = [ "libc", "libdyld", "libdwarf", + "libio", "libunwind", "runtime", + "satman" ] [profile.release] diff --git a/src/Makefile b/src/Makefile index e2dc094..5eca52f 100644 --- a/src/Makefile +++ b/src/Makefile @@ -1,16 +1,18 @@ TARGET := zc706 GWARGS := -V simple -all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin +all: runtime + +runtime: ../build/runtime.bin .PHONY: all ../build/pl.rs ../build/rustc-cfg: gateware/* mkdir -p ../build - python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg $(GWARGS) + python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -m ../build/mem.rs $(GWARGS) -../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg $(shell find . -print) +../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg cd runtime && \ XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \ cargo xbuild --release \ @@ -19,3 +21,13 @@ all: ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin ../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin + +satmanout: ../build/pl.rs ../build/rustc-cfg + cd satman && \ + XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \ + cargo xbuild --release \ + --target-dir ../../build/firmware \ + --no-default-features --features=target_$(TARGET) + +satman: satmanout + llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/satman ../build/satman.bin \ No newline at end of file -- 2.42.0 From ab3ac796554ceddc37950b987b910dcb62cba8cb Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 5 Oct 2021 15:50:16 +0200 Subject: [PATCH 2/8] zc706 nist clock: started rtio channel changes --- src/gateware/zc706.py | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 766cab5..33a69fc 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -163,10 +163,6 @@ class NIST_CLOCK(ZC706): rtio_channels = [] - for i in range(4): - phy = ttl_simple.Output(platform.request("user_led_33", i)) - self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy)) for i in range(16): if i % 4 == 3: @@ -183,16 +179,42 @@ class NIST_CLOCK(ZC706): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) + # todo: figure out pins for that on zc706 + # phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) + # self.submodules += phy + # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) + + # could check the LED # + phy = ttl_simple.Output(platform.request("user_led_33", 2)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + ams101_dac = self.platform.request("ams101_dac", 0) + phy = ttl_simple.Output(ams101_dac.ldac) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) + phy = spi2.SPIMaster(ams101_dac) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy( + phy, ififo_depth=4)) + for i in range(3): phy = spi2.SPIMaster(self.platform.request("spi", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=128)) + # todo check sdcard spi pins on zc706 (if applicable) + # phy = spi2.SPIMaster(platform.request("sdcard_spi_33")) + # self.submodules += phy + # rtio_channels.append(rtio.Channel.from_phy( + # phy, ififo_depth=4)) + phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) -- 2.42.0 From 0f0f0f898671a68f1c62ad9d6845408a9220adce Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 6 Oct 2021 15:01:22 +0200 Subject: [PATCH 3/8] rearranged rtio for nist qc2 --- src/gateware/zc706.py | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 33a69fc..52dda90 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -189,19 +189,19 @@ class NIST_CLOCK(ZC706): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - ams101_dac = self.platform.request("ams101_dac", 0) - phy = ttl_simple.Output(ams101_dac.ldac) - self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy)) + # ams101_dac = self.platform.request("ams101_dac", 0) + # phy = ttl_simple.Output(ams101_dac.ldac) + # self.submodules += phy + # rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - phy = spi2.SPIMaster(ams101_dac) - self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy( - phy, ififo_depth=4)) + # phy = spi2.SPIMaster(ams101_dac) + # self.submodules += phy + # rtio_channels.append(rtio.Channel.from_phy( + # phy, ififo_depth=4)) for i in range(3): phy = spi2.SPIMaster(self.platform.request("spi", i)) @@ -239,23 +239,36 @@ class NIST_QC2(ZC706): rtio_channels = [] - for i in range(4): - phy = ttl_simple.Output(platform.request("user_led_33", i)) - self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy)) - # All TTL channels are In+Out capable for i in range(40): phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) + # phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) + # self.submodules += phy + # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) + + phy = ttl_simple.Output(platform.request("user_led_33", 2)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + # ams101_dac = self.platform.request("ams101_dac", 0) + # phy = ttl_simple.Output(ams101_dac.ldac) + # self.submodules += phy + # rtio_channels.append(rtio.Channel.from_phy(phy)) + # CLK0, CLK1 are for clock generators, on backplane SMP connectors for i in range(2): phy = ttl_simple.ClockGen( platform.request("clkout", i)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) + + # phy = spi2.SPIMaster(ams101_dac) + # self.submodules += phy + # rtio_channels.append(rtio.Channel.from_phy( + # phy, ififo_depth=4)) for i in range(4): phy = spi2.SPIMaster(self.platform.request("spi", i)) -- 2.42.0 From a20598da78bc68053c4aa0c40d3f80b7ff232dc6 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 6 Oct 2021 15:32:17 +0200 Subject: [PATCH 4/8] verified missing pins in zc706 docs, added ams, sd --- src/gateware/zc706.py | 67 ++++++++++++++++++++++++++++--------------- 1 file changed, 44 insertions(+), 23 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 52dda90..a6cd746 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -149,6 +149,26 @@ leds_fmc33 = [ ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")), ] +# todo: verify if gpio pins/expansion port on xadc is the same as on kc705 +_ams101_dac = [ + ("ams101_dac", 0, + Subsignal("ldac", Pins("XADC:GPIO0")), + Subsignal("clk", Pins("XADC:GPIO1")), + Subsignal("mosi", Pins("XADC:GPIO2")), + Subsignal("cs_n", Pins("XADC:GPIO3")), + IOStandard("LVTTL") + ) +] + +_sdcard_spi_33 = [ + ("sdcard_spi_33", 0, + Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")), + Subsignal("clk", Pins("B20")), + Subsignal("mosi", Pins("J18")), + Subsignal("cs_n", Pins("H18")), + IOStandard("LVCMOS33") + ) +] class NIST_CLOCK(ZC706): """ @@ -160,10 +180,11 @@ class NIST_CLOCK(ZC706): platform = self.platform platform.add_extension(nist_clock.fmc_adapter_io) platform.add_extension(leds_fmc33) + platform.add_extension(_ams101_dac) + platform.add_extension(_sdcard_spi_33) rtio_channels = [] - for i in range(16): if i % 4 == 3: phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i)) @@ -179,7 +200,7 @@ class NIST_CLOCK(ZC706): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) - # todo: figure out pins for that on zc706 + # todo: figure out what to do since zc706 has no SMA I/O # phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) # self.submodules += phy # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) @@ -189,19 +210,19 @@ class NIST_CLOCK(ZC706): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - # ams101_dac = self.platform.request("ams101_dac", 0) - # phy = ttl_simple.Output(ams101_dac.ldac) - # self.submodules += phy - # rtio_channels.append(rtio.Channel.from_phy(phy)) + ams101_dac = self.platform.request("ams101_dac", 0) + phy = ttl_simple.Output(ams101_dac.ldac) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) phy = ttl_simple.ClockGen(platform.request("la32_p")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - # phy = spi2.SPIMaster(ams101_dac) - # self.submodules += phy - # rtio_channels.append(rtio.Channel.from_phy( - # phy, ififo_depth=4)) + phy = spi2.SPIMaster(ams101_dac) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy( + phy, ififo_depth=4)) for i in range(3): phy = spi2.SPIMaster(self.platform.request("spi", i)) @@ -209,11 +230,10 @@ class NIST_CLOCK(ZC706): rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=128)) - # todo check sdcard spi pins on zc706 (if applicable) - # phy = spi2.SPIMaster(platform.request("sdcard_spi_33")) - # self.submodules += phy - # rtio_channels.append(rtio.Channel.from_phy( - # phy, ififo_depth=4)) + phy = spi2.SPIMaster(platform.request("sdcard_spi_33")) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy( + phy, ififo_depth=4)) phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy @@ -236,6 +256,7 @@ class NIST_QC2(ZC706): platform = self.platform platform.add_extension(nist_qc2.fmc_adapter_io) platform.add_extension(leds_fmc33) + platform.add_extension(_ams101_dac) rtio_channels = [] @@ -253,10 +274,10 @@ class NIST_QC2(ZC706): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - # ams101_dac = self.platform.request("ams101_dac", 0) - # phy = ttl_simple.Output(ams101_dac.ldac) - # self.submodules += phy - # rtio_channels.append(rtio.Channel.from_phy(phy)) + ams101_dac = self.platform.request("ams101_dac", 0) + phy = ttl_simple.Output(ams101_dac.ldac) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) # CLK0, CLK1 are for clock generators, on backplane SMP connectors for i in range(2): @@ -265,10 +286,10 @@ class NIST_QC2(ZC706): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - # phy = spi2.SPIMaster(ams101_dac) - # self.submodules += phy - # rtio_channels.append(rtio.Channel.from_phy( - # phy, ififo_depth=4)) + phy = spi2.SPIMaster(ams101_dac) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy( + phy, ififo_depth=4)) for i in range(4): phy = spi2.SPIMaster(self.platform.request("spi", i)) -- 2.42.0 From bbb8c59ade5d172d59d67785b2b54185af49e015 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 13 Oct 2021 16:04:40 +0800 Subject: [PATCH 5/8] replaced sma gpio with pmod1_0 --- src/gateware/zc706.py | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index f492823..73746c9 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -88,6 +88,17 @@ si5324_fmc33 = [ ), ] +pmod1_33 = [ + ("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")), + ("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")), + ("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")), + ("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")), + ("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")), + ("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")), + ("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")), + ("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")), +] + def prepare_zc706_platform(platform): platform.toolchain.bitstream_commands.extend([ @@ -464,6 +475,7 @@ class _NIST_CLOCK_RTIO: platform = self.platform platform.add_extension(nist_clock.fmc_adapter_io) platform.add_extension(leds_fmc33) + platform.add_extension(pmod1_33) platform.add_extension(_ams101_dac) platform.add_extension(_sdcard_spi_33) @@ -484,10 +496,10 @@ class _NIST_CLOCK_RTIO: self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) - # todo: figure out what to do since zc706 has no SMA I/O - # phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) - # self.submodules += phy - # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) + # no SMA GPIO, replaced with PMOD1_0 + phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) # could check the LED # phy = ttl_simple.Output(platform.request("user_led_33", 2)) @@ -548,9 +560,10 @@ class _NIST_QC2_RTIO: self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) - # phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33")) - # self.submodules += phy - # rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) + # no SMA GPIO, replaced with PMOD1_0 + phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) phy = ttl_simple.Output(platform.request("user_led_33", 2)) self.submodules += phy -- 2.42.0 From d1d1bd2f1a3754aa0aa78e96a7e6a5b24bde1dbd Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 13 Oct 2021 16:11:27 +0800 Subject: [PATCH 6/8] not sure where the change came from in local_run --- local_run.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/local_run.sh b/local_run.sh index f72d223..1e01fe0 100755 --- a/local_run.sh +++ b/local_run.sh @@ -58,4 +58,4 @@ else load_bitstream_cmd="-g $result_dir/top.bit" fi artiq_netboot $load_bitstream_cmd -f $result_dir/$fwtype.bin -b $board_host -fi +fi \ No newline at end of file -- 2.42.0 From afe3c165da4af89a9162090567e7e8c30ba1abcd Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 13 Oct 2021 16:14:09 +0800 Subject: [PATCH 7/8] moved 3.3v signals to one place, removed duplicate --- src/gateware/zc706.py | 48 +++++++++++++++++-------------------------- 1 file changed, 19 insertions(+), 29 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 73746c9..b07977b 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -99,6 +99,25 @@ pmod1_33 = [ ("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")), ] +_ams101_dac = [ + ("ams101_dac", 0, + Subsignal("ldac", Pins("XADC:GPIO0")), + Subsignal("clk", Pins("XADC:GPIO1")), + Subsignal("mosi", Pins("XADC:GPIO2")), + Subsignal("cs_n", Pins("XADC:GPIO3")), + IOStandard("LVTTL") + ) +] + +_sdcard_spi_33 = [ + ("sdcard_spi_33", 0, + Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")), + Subsignal("clk", Pins("B20")), + Subsignal("mosi", Pins("J18")), + Subsignal("cs_n", Pins("H18")), + IOStandard("LVCMOS33") + ) +] def prepare_zc706_platform(platform): platform.toolchain.bitstream_commands.extend([ @@ -437,35 +456,7 @@ class _SatelliteBase(SoCCore): self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") -# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply. -# This also changes the I/O standard for some on-board LEDs. -leds_fmc33 = [ - ("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")), - ("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")), - ("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")), - ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")), -] -# todo: verify if gpio pins/expansion port on xadc is the same as on kc705 -_ams101_dac = [ - ("ams101_dac", 0, - Subsignal("ldac", Pins("XADC:GPIO0")), - Subsignal("clk", Pins("XADC:GPIO1")), - Subsignal("mosi", Pins("XADC:GPIO2")), - Subsignal("cs_n", Pins("XADC:GPIO3")), - IOStandard("LVTTL") - ) -] - -_sdcard_spi_33 = [ - ("sdcard_spi_33", 0, - Subsignal("miso", Pins("D20"), Misc("PULLUP=TRUE")), - Subsignal("clk", Pins("B20")), - Subsignal("mosi", Pins("J18")), - Subsignal("cs_n", Pins("H18")), - IOStandard("LVCMOS33") - ) -] class _NIST_CLOCK_RTIO: """ @@ -501,7 +492,6 @@ class _NIST_CLOCK_RTIO: self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) - # could check the LED # phy = ttl_simple.Output(platform.request("user_led_33", 2)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) -- 2.42.0 From 5e25f3016fc6eb6a32260930c7d09031e236d5b6 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Wed, 13 Oct 2021 16:36:01 +0800 Subject: [PATCH 8/8] changed user led for nist rtio to 0 --- src/gateware/zc706.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index b07977b..a03ef77 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -492,7 +492,7 @@ class _NIST_CLOCK_RTIO: self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) - phy = ttl_simple.Output(platform.request("user_led_33", 2)) + phy = ttl_simple.Output(platform.request("user_led_33", 0)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) @@ -555,7 +555,7 @@ class _NIST_QC2_RTIO: self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) - phy = ttl_simple.Output(platform.request("user_led_33", 2)) + phy = ttl_simple.Output(platform.request("user_led_33", 0)) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) -- 2.42.0