M-Labs/artiq-zynq
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117_rtio_channels #147

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sb10q merged 10 commits from mwojcik/artiq-zynq:117_rtio_channels into master 2021-10-13 17:20:25 +08:00
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1 changed files with 26 additions and 4 deletions
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src/gateware/zc706.py
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@ -163,10 +163,6 @@ class NIST_CLOCK(ZC706):
rtio_channels = [] rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led_33", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for i in range(16): for i in range(16):
if i % 4 == 3: if i % 4 == 3:
@ -183,16 +179,42 @@ class NIST_CLOCK(ZC706):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# todo: figure out pins for that on zc706
# phy = ttl_serdes_7series.InOut_8X(platform.request("user_sma_gpio_n_33"))
# self.submodules += phy
# rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# could check the LED #
phy = ttl_simple.Output(platform.request("user_led_33", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
ams101_dac = self.platform.request("ams101_dac", 0)
phy = ttl_simple.Output(ams101_dac.ldac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
phy = ttl_simple.ClockGen(platform.request("la32_p")) phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
phy = spi2.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=4))
for i in range(3): for i in range(3):
phy = spi2.SPIMaster(self.platform.request("spi", i)) phy = spi2.SPIMaster(self.platform.request("spi", i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy( rtio_channels.append(rtio.Channel.from_phy(
phy, ififo_depth=128)) phy, ififo_depth=128))
# todo check sdcard spi pins on zc706 (if applicable)
# phy = spi2.SPIMaster(platform.request("sdcard_spi_33"))
# self.submodules += phy
# rtio_channels.append(rtio.Channel.from_phy(
# phy, ififo_depth=4))
phy = dds.AD9914(platform.request("dds"), 11, onehot=True) phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))