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19 Commits (14fa038118884f807c4680c128a12b0148ca7fd5)

Author SHA1 Message Date
morgan 14fa038118 Firmware: Runtime WRPLL 
runtime: drive CLK_SEL to true when si549 is used
runtime & libboard_artiq: allow standalone to use io_expander
si549: add bit bang mmcm dynamic configuration
si549: add frequency counter for refclk
rtio_clocking & si549: add 125Mhz wrpll refclk setup
 2024-04-12 16:38:46 +08:00
linuswck a4d1be00c0 Firmware: Add drtio_eem.rs support 
- Port from Artiq repo
- Initialize the drtio_eem on main, rtio_clocking
- Driver for eem_transceiver
 2023-10-10 11:22:05 +08:00
mwojcik 623cc7b79e libkernel -> ksupport 2023-10-09 11:42:51 +08:00
mwojcik 6885c618b5 move kernel-related code to separate library 2023-10-09 11:36:23 +08:00
mwojcik ecd4ca333c rtio_clocking: inform the user if PLL is bypassed 2023-10-06 16:27:25 +08:00
mwojcik 49810da188 runtime: wait longer for PLL lock 2023-10-05 12:17:43 +08:00
linuswck 4ae8557018 drtio: remame drtio_transceiver to gt_drtio 
Co-authored-by: linuswck <linuswck@m-labs.hk>
Co-committed-by: linuswck <linuswck@m-labs.hk>
 2023-08-28 13:05:40 +08:00
Egor Savkin c6fcc4e351 Add ext0_synth0_80to125 option to the clocker config 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-04-13 12:08:25 +08:00
Egor Savkin a519d24074 firmware: create and apply rustfmt policy 
Co-authored-by: Egor Savkin <es@m-labs.hk>
Co-committed-by: Egor Savkin <es@m-labs.hk>
 2023-02-22 11:02:43 +08:00
mwojcik 46b2687d70 RTIO/SYS Clock merge 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2023-02-17 15:52:43 +08:00
David Nadlinger 8e0229d265 si5324: crystal_{ref -> as_ckin2} [nfc] 
This makes it clear that by itself, the flag does not
cause the input mux to be changed.
 2022-12-17 01:33:50 +00:00
David Nadlinger 2ddb4d259f Undo most of Si5324 unification (5c054cc901) 
This reverts most of 5c054cc901, as it turns out that
si5324::setup is in fact also used to configure the
chip for operation as a DRTIO satellite.
 2022-12-17 01:31:14 +00:00
David Nadlinger 5c054cc901 Unify Si5324 setup code with main ARTIQ repository [nfc] 
I chose the version from the main repository for two
reasons:
 - Explicitly specifying si5324_ref_input every time would
   not work for the different Kasli/… hardware versions.
 - Having `crystal_ref` as a setting in the configuration
   is misleading if it does not actually activate the crystal
   for use as a reference (but rather does
   `route_crystal_to_ckin2`).

Related m-labs/artiq commits:
 - 740543d4e284245248e3ff838c46505938dcae7a
 - 3c7a394eff553ab75a7ea78bdd17830366504dc6
 2022-12-12 23:22:01 +00:00
mwojcik c834e4f503 enable network and mgmt during Rust panic, make RTIO PLL lock failure a panic 
Closes #198 #200

Making it a soft panic makes it more involved with a bit of code duplication - setting up mgmt requires setting up the interface and sockets. Maybe can be done a bit cleaner.

```
[spaqin@hera:~/m-labs/artiq-zynq]$ artiq_sinara_tester
****** Sinara system tester ******
[...]
ConnectionRefusedError: [Errno 111] Connection refused

[spaqin@hera:~/m-labs/artiq-zynq]$ artiq_coremgmt -D 192.168.1.56 log
[     0.000067s]  INFO(runtime): NAR3/Zynq7000 starting...
[     0.005238s]  INFO(runtime): detected gateware: GenericMaster
[     0.016152s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.023004s]  WARN(runtime): config initialization failed: SD error: Card initialization error: No card inserted, check if the card is inserted properly.
[     0.036730s]  WARN(runtime::rtio_clocking): error reading configuration. Falling back to default.
[     0.213000s] ERROR(runtime::rtio_clocking): RTIO PLL failed to lock
[     0.224443s]  INFO(libboard_zynq::i2c): PCA9548 detected
[     0.256197s]  INFO(runtime::comms): network addresses: MAC=e8-eb-1b-13-49-8b IPv4=192.168.1.56 IPv6-LL=fe80::eaeb:1bff:fe13:498b IPv6: no configured address
[     0.270183s] ERROR(runtime::comms): There has been an error configuring the device: RTIO PLL failed to lock. Only mgmt interface will be available.
[     4.000095s]  INFO(libboard_zynq::eth): eth: got Link { speed: S1000, duplex: Full }
[    33.148521s]  INFO(runtime::mgmt): received connection
```

Reviewed-on: #199
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2022-10-21 17:56:34 +08:00
mwojcik 78bc162749 rtio_clocking: remove loop 2022-04-12 13:33:52 +08:00
occheung 6c834899e9 si5324: fix clock source 2022-03-09 13:55:36 +08:00
spaqin 4f2a0986da rtio_clocking: fix wrong descriptions 2022-03-03 10:24:13 +08:00
mwojcik 31fb2b388a Support for DRTIO 100MHz (#155) 
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-12-03 17:19:42 +08:00
mwojcik 8be5048cd3 upgrade to new clock configuration system (#152) 
As mentioned in https://github.com/m-labs/artiq/issues/1735 - this is the Zynq version.

Reviewed-on: #152
Co-authored-by: mwojcik <mw@m-labs.hk>
Co-committed-by: mwojcik <mw@m-labs.hk>
 2021-11-29 11:17:59 +08:00