Commit Graph

24 Commits

Author SHA1 Message Date
85f7b2bf15 use overlay instead of passing llvm/rustc/cargo around 2019-06-06 12:05:48 +08:00
f707295646 use the GNU linker 2019-06-06 00:07:53 +08:00
aa1c3726f3 attempt to use lld linker 2019-06-05 23:46:29 +08:00
d5c288c20b rustc: disable lld 2019-06-05 23:42:39 +08:00
1361c6ae9e Revert "llvm: only build x86 and riscv"
This reverts commit b17ec6fb1f.
2019-06-05 23:41:22 +08:00
b17ec6fb1f llvm: only build x86 and riscv
Attempting to fix llvm-lld breakage on msp430 by disabling msp430.
2019-06-05 23:19:51 +08:00
6ad1d993c6 rustc: remove riscv32i support 2019-06-05 23:07:49 +08:00
f929be260a build cargo 2019-06-05 23:06:57 +08:00
2c3fc22963 Use riscv32imc for Rust core crate
Some other crates have issues with riscv32i.
2019-06-05 23:06:03 +08:00
14c7b4890c rustc: enable lld 2019-06-05 23:05:15 +08:00
9e93a9cf39 rustc: make llvm override compatible with nixos-unstable 2019-05-14 19:17:16 +08:00
9f4538555e fix previous commit 2019-05-14 19:16:52 +08:00
e9b005d50a mark riscv rustc 2019-05-14 19:05:30 +08:00
677ddefff2 mark riscv llvm 2019-05-14 14:07:36 +08:00
351d5360f0 llvm -> llvm_7 for nixos-unstable rustc 2019-05-14 10:41:10 +08:00
e3f47815e5 rust: add riscv32i 2019-04-09 00:48:19 +08:00
25fe837684 use upstream rust/llvm 2019-04-09 00:09:58 +08:00
b913a92a82 add rustc (WIP) 2019-04-06 18:23:31 +08:00
1bf9b5eb2b add VexRiscv 2019-04-05 18:58:11 +08:00
584dba9ed0 add scala-spinalhdl 2019-04-04 23:44:07 +08:00
466d85e719 reorganize 2019-04-01 11:05:08 +08:00
472114c136 add binutils 2019-03-27 16:55:36 +08:00
ed53324019 add LLVM and Clang 2019-03-27 16:42:07 +08:00
38ccee5c01 reorganize Nix files to expose lib functions and derivations properly 2019-03-25 16:07:50 +08:00