Sebastien Bourdeauducq
b17ec6fb1f
Attempting to fix llvm-lld breakage on msp430 by disabling msp430.
35 lines
1.5 KiB
Nix
35 lines
1.5 KiB
Nix
{ pkgs }:
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rec {
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yosys = pkgs.callPackage ./eda/yosys.nix {};
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symbiyosys = pkgs.symbiyosys.override { inherit yosys; };
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nmigen = pkgs.callPackage ./eda/nmigen.nix { inherit yosys; };
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scala-spinalhdl = pkgs.callPackage ./eda/scala-spinalhdl.nix {};
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jtagtap = pkgs.callPackage ./cores/jtagtap.nix { inherit nmigen; };
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minerva = pkgs.callPackage ./cores/minerva.nix { inherit nmigen; inherit jtagtap; };
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vexriscv-small = pkgs.callPackage ./cores/vexriscv.nix {
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inherit scala-spinalhdl;
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name = "vexriscv-small";
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scalaToRun = "vexriscv.demo.GenSmallAndProductive";
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};
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heavycomps = pkgs.callPackage ./heavycomps.nix { inherit nmigen; };
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binutils-riscv = pkgs.callPackage ./compilers/binutils.nix { platform = "riscv32"; };
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llvm_7 = pkgs.llvm_7.overrideAttrs(oa: {
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name = oa.name + "-riscv";
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cmakeFlags = oa.cmakeFlags ++ ["-DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=RISCV" "-DLLVM_TARGETS_TO_BUILD=X86"];
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});
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rustc = (pkgs.rustc.overrideAttrs(oa: {
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name = "${oa.pname}-${oa.version}-riscv";
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configureFlags = oa.configureFlags ++ [ "--enable-lld" ];
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})).override {
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inherit llvm_7;
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pkgsBuildBuild = pkgs.pkgsBuildBuild // { inherit llvm_7; };
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pkgsBuildHost = pkgs.pkgsBuildHost // { inherit llvm_7; };
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pkgsBuildTarget = pkgs.pkgsBuildTarget // { inherit llvm_7; };
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};
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rust-riscv32imc-crates = pkgs.callPackage ./compilers/rust-riscv32imc-crates.nix { inherit rustc; };
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cargo = pkgs.cargo.override { inherit rustc; };
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}
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