 harry
|
f7f933b351
|
update README
|
2020-04-30 16:47:30 +08:00 |
|
Harry Ho
|
b872a72866
|
fix GPIO CSR issue; add "invert" option
|
2020-04-29 12:51:15 +08:00 |
|
Harry Ho
|
353b34a135
|
implement UART, Timer, SPI Flash & Eth RGMII cores
* These implementations use Harry's proposal for nmigen-stdio & nmigen-soc
|
2020-03-02 19:55:22 +08:00 |
|
Harry Ho
|
2cb3484e33
|
update nmigen-boards
|
2019-11-04 09:32:32 +08:00 |
 Sebastien Bourdeauducq
|
e51524d3f5
|
update vivado
|
2019-11-03 15:02:48 +08:00 |
|
Harry Ho
|
5d88fd2aa4
|
fix styling
|
2019-10-17 17:35:29 +08:00 |
|
harry
|
9710ebd9d5
|
upgrade nix scripts & example codes to use nmigen-v0.1rc1 (#1)
|
2019-10-17 15:55:49 +08:00 |
|
Sebastien Bourdeauducq
|
2281c620ce
|
add development shell.nix
|
2019-07-29 15:09:10 +08:00 |
|
Sebastien Bourdeauducq
|
12032433ed
|
use nixpkgs 19.03
* too much breakage on nixos-unstable
* we should track upstream yosys/nextpnr more closely than nixpkgs does
|
2019-07-29 14:58:46 +08:00 |
|
Sebastien Bourdeauducq
|
87acbacf87
|
firmware: prevent Nix from corrupting output ELF
|
2019-07-29 13:58:21 +08:00 |
|
Sebastien Bourdeauducq
|
3deb18c261
|
nmigen: fix hash
|
2019-07-24 15:50:54 +08:00 |
|
Sebastien Bourdeauducq
|
98ca78220a
|
nmigen: bump
|
2019-07-08 10:14:18 +08:00 |
|
Sebastien Bourdeauducq
|
c11d5582ef
|
nmigen: bump
|
2019-07-03 21:31:27 +08:00 |
|
Sebastien Bourdeauducq
|
af51f6fe8f
|
use nmigen build system, upstream yosys, reorganize
|
2019-07-03 18:51:54 +08:00 |
|
Sebastien Bourdeauducq
|
ca293ee7cc
|
nmigen-boards: bump
|
2019-07-03 18:04:50 +08:00 |
|
Sebastien Bourdeauducq
|
5d5853d3f8
|
examples/helloworld: use new nmigen read_port comb API
|
2019-07-03 11:29:07 +08:00 |
|
Sebastien Bourdeauducq
|
1c0c4cee1b
|
nmigen: bump
|
2019-07-03 11:27:46 +08:00 |
|
Sebastien Bourdeauducq
|
68e1b1e778
|
nmigen-boards: bump
|
2019-07-03 09:05:33 +08:00 |
|
Sebastien Bourdeauducq
|
2f200bbf8a
|
nmigen: bump
|
2019-07-03 09:00:24 +08:00 |
|
Sebastien Bourdeauducq
|
29548b4a33
|
nmigen: fix hash
|
2019-06-29 13:27:55 +08:00 |
|
Sebastien Bourdeauducq
|
466eed2df9
|
README: add nMigen link
|
2019-06-24 18:26:44 +08:00 |
|
Sebastien Bourdeauducq
|
87b4b357c3
|
README: add some details
|
2019-06-24 18:25:44 +08:00 |
|
Sebastien Bourdeauducq
|
8d327d4f6f
|
nmigen: bump
|
2019-06-13 13:46:18 +08:00 |
|
Sebastien Bourdeauducq
|
4af5e6fb9e
|
add experimental LiteDRAM package
|
2019-06-13 09:36:12 +08:00 |
|
Sebastien Bourdeauducq
|
4c7ca4a8d1
|
add experimental LiteX package
|
2019-06-12 17:22:54 +08:00 |
|
Sebastien Bourdeauducq
|
92671d534c
|
nmigen-boards: add
|
2019-06-11 22:53:03 +08:00 |
|
Sebastien Bourdeauducq
|
6d837f4662
|
nmigen: bump
|
2019-06-11 22:52:43 +08:00 |
|
Sebastien Bourdeauducq
|
6d2449b973
|
nmigen: fix URL
|
2019-06-11 22:47:38 +08:00 |
|
Sebastien Bourdeauducq
|
b93ee35a7d
|
update README
|
2019-06-10 15:01:58 +08:00 |
|
Sebastien Bourdeauducq
|
0bb4a0da46
|
more markdown fixing
|
2019-06-10 14:51:34 +08:00 |
|
Sebastien Bourdeauducq
|
630048ae5f
|
gitea doesn't like rst
|
2019-06-10 14:51:07 +08:00 |
|
Sebastien Bourdeauducq
|
40f869632b
|
document how to build helloworld soc
|
2019-06-10 14:49:55 +08:00 |
|
Sebastien Bourdeauducq
|
3598e08212
|
symbiflow: 100MHz timing (HACK)
|
2019-06-09 00:06:17 +08:00 |
|
Sebastien Bourdeauducq
|
d9b42a0807
|
clean up firmware compilation
|
2019-06-09 00:05:40 +08:00 |
|
Sebastien Bourdeauducq
|
fd05fa560f
|
firmware: compile for riscv32i
|
2019-06-08 23:01:37 +08:00 |
|
Sebastien Bourdeauducq
|
328a521632
|
simplesoc_ecp5: run simulation longer
|
2019-06-08 23:00:57 +08:00 |
|
Sebastien Bourdeauducq
|
c7bda2b144
|
compile Rust core crate for riscv32i
|
2019-06-08 21:52:33 +08:00 |
|
Sebastien Bourdeauducq
|
03dc4f6e32
|
add RISCV GCC
Needed to refresh riscv and riscv-rt Rust crates.
|
2019-06-08 21:50:47 +08:00 |
|
Sebastien Bourdeauducq
|
033659344f
|
Revert "Revert "reinstate riscv32i""
Custom rustc targets with JSON come with a messed up TARGET environment variable and lots of things break.
This reverts commit b22d85ba52.
|
2019-06-08 19:31:41 +08:00 |
|
Sebastien Bourdeauducq
|
8388018db7
|
also build riscv64 binutils
|
2019-06-08 19:25:38 +08:00 |
|
Sebastien Bourdeauducq
|
b22d85ba52
|
Revert "reinstate riscv32i"
This reverts commit 06d825f63d.
|
2019-06-08 18:48:50 +08:00 |
|
Sebastien Bourdeauducq
|
06d825f63d
|
reinstate riscv32i
|
2019-06-08 17:35:27 +08:00 |
|
Sebastien Bourdeauducq
|
75e9310097
|
simplesoc_ecp5: add simulation
|
2019-06-08 17:30:49 +08:00 |
|
Sebastien Bourdeauducq
|
83ffe66f70
|
simplesoc_ecp5: add blinking LED
|
2019-06-07 23:17:19 +08:00 |
|
Sebastien Bourdeauducq
|
2cfafcdf20
|
firmware: match simplesoc memory addresses
|
2019-06-07 23:17:03 +08:00 |
|
Sebastien Bourdeauducq
|
ad4f00e93d
|
simplesoc_ecp5: load firmware
|
2019-06-06 18:11:54 +08:00 |
|
Sebastien Bourdeauducq
|
a53c470d17
|
nmigen: bump
|
2019-06-06 18:11:31 +08:00 |
|
Sebastien Bourdeauducq
|
713f644072
|
minerva: bump
|
2019-06-06 18:04:56 +08:00 |
|
Sebastien Bourdeauducq
|
a203307108
|
reorganize
|
2019-06-06 17:25:11 +08:00 |
|
Sebastien Bourdeauducq
|
63664ab959
|
build .bin firmware image
|
2019-06-06 17:17:45 +08:00 |