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update README

core_lib
harry 1 year ago
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      README.md

8
README.md

@ -3,9 +3,7 @@ HeavyX
A FPGA SoC framework embracing cutting-edge open source technologies (nMigen, Yosys, SymbiFlow, Minerva, Nix, Rust).
This is work in progress!
"Hello World" SoC demo
SoC demo
----------------------
Softcore system-on-chip on the Lattice ECP5 Versa board, built with a 100% Verilog/VHDL-free and 100% open source toolchain.
@ -13,7 +11,7 @@ Softcore system-on-chip on the Lattice ECP5 Versa board, built with a 100% Veril
* Everything written in nMigen (https://github.com/m-labs/nmigen/).
* RISC-V 32-bit pipelined core (Minerva by Lambdaconcept).
* 100MHz clock frequency.
* Runs a Rust "hello world" program.
* Runs a Rust program controlling the UART, SPI flash, Ethernet and GPIO.
Use nixpkgs 19.03. If you are unfamiliar with Nix and just installed it on another (non-NixOS) distribution, simply run:
@ -32,7 +30,7 @@ substituters = https://cache.nixos.org https://nixbld.m-labs.hk
trusted-public-keys = cache.nixos.org-1:6NCHdD59X431o0gWypbMrAURkbJ16ZPMQFGspcDShjY= nixbld.m-labs.hk-1:5aSRVA5b320xbNvu30tqxVPXpld73bhtOeH6uAjRyHc=
```
Run ``nix-build -A simplesoc_ecp5 release.nix``
Run ``nix-build -A testing_ecp5 release.nix``
You can also build manually and use your distribution's packages, but YMMV.

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