forked from M-Labs/artiq-zynq
47 lines
1.9 KiB
Python
47 lines
1.9 KiB
Python
"""Auxiliary controller, common to satellite and master"""
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from artiq.gateware.drtio.aux_controller import Transmitter, Receiver
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from migen.fhdl.simplify import FullMemoryWE
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from misoc.interconnect.csr import *
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from migen_axi.interconnect.sram import SRAM
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from migen_axi.interconnect import axi
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max_packet = 1024
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# TODO: FullMemoryWE should be applied by migen.build
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@FullMemoryWE()
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class DRTIOAuxControllerAxi(Module):
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def __init__(self, link_layer):
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self.bus = axi.Interface()
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self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
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self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
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tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
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rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
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wsb = log2_int(len(self.bus.w.data)//8)
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aw_decoder = axi.AddressDecoder(self.bus.aw,
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[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.aw),
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(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.aw)],
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register=True)
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ar_decoder = axi.AddressDecoder(self.bus.ar,
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[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.ar),
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(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.ar)],
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register=True)
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self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
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def get_csrs(self):
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return self.transmitter.get_csrs() + self.receiver.get_csrs()
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@FullMemoryWE()
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class DRTIOAuxControllerBare(Module):
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# Barebones version of the AuxController. No SRAM, no decoders.
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# add memories manually from tx and rx in target code.
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def __init__(self, link_layer):
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self.bus = axi.Interface()
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self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
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self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
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def get_csrs(self):
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return self.transmitter.get_csrs() + self.receiver.get_csrs()
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