"""Auxiliary controller, common to satellite and master"""

from artiq.gateware.drtio.aux_controller import Transmitter, Receiver
from migen.fhdl.simplify import FullMemoryWE
from misoc.interconnect.csr import *
from migen_axi.interconnect.sram import SRAM
from migen_axi.interconnect import axi

max_packet = 1024


# TODO: FullMemoryWE should be applied by migen.build
@FullMemoryWE()
class DRTIOAuxControllerAxi(Module):
    def __init__(self, link_layer):
        self.bus = axi.Interface()
        self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
        self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))

        tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
        rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
        wsb = log2_int(len(self.bus.w.data)//8)
        aw_decoder = axi.AddressDecoder(self.bus.aw,
            [(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.aw),
             (lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.aw)],
            register=True)
        ar_decoder = axi.AddressDecoder(self.bus.ar,
            [(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.ar),
             (lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.ar)],
            register=True)
        self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder

    def get_csrs(self):
        return self.transmitter.get_csrs() + self.receiver.get_csrs()

@FullMemoryWE()
class DRTIOAuxControllerBare(Module):
    # Barebones version of the AuxController. No SRAM, no decoders.
    # add memories manually from tx and rx in target code.
    def __init__(self, link_layer):
        self.bus = axi.Interface()
        self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
        self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))

    def get_csrs(self):
        return self.transmitter.get_csrs() + self.receiver.get_csrs()