mwojcik d3152f3d24 changed auxctrl tx/rx memory to axi2csr_sram		2021-09-10 15:25:05 +02:00
..
acpki.py	acpki: working	2020-09-09 21:24:49 +08:00
analyzer.py	analyzer: report AXI bus errors	2020-07-20 19:51:22 +08:00
aux_controller.py	changed auxctrl tx/rx memory to axi2csr_sram	2021-09-10 15:25:05 +02:00
dma.py	dma: report AXI bus error	2020-07-21 12:47:20 +08:00
endianness.py	dma: fix endianness issues	2020-07-16 17:27:08 +08:00
kasli_soc.py	changed auxctrl tx/rx memory to axi2csr_sram	2021-09-10 15:25:05 +02:00
test_dma.py	dma: fix endianness issues	2020-07-16 17:27:08 +08:00
zc706.py	changed auxctrl tx/rx memory to axi2csr_sram	2021-09-10 15:25:05 +02:00