diff --git a/src/gateware/aux_controller.py b/src/gateware/aux_controller.py
index 4f3891b0..fc667b7d 100644
--- a/src/gateware/aux_controller.py
+++ b/src/gateware/aux_controller.py
@@ -72,7 +72,7 @@ class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
 
 
 @FullMemoryWE()
-class DRTIOAuxControllerBare(Module):
+class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
     # Barebones version of the AuxController. No SRAM, no decoders.
     # add memories manually from tx and rx in target code.
     def get_tx_port(self):