From db1c9d336e13035228c6534f502aa226ac09ab93 Mon Sep 17 00:00:00 2001
From: mwojcik <mw@m-labs.hk>
Date: Mon, 4 Oct 2021 08:53:38 +0200
Subject: [PATCH] aux_controller: fix class parent

---
 src/gateware/aux_controller.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gateware/aux_controller.py b/src/gateware/aux_controller.py
index 4f3891b0..fc667b7d 100644
--- a/src/gateware/aux_controller.py
+++ b/src/gateware/aux_controller.py
@@ -72,7 +72,7 @@ class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
 
 
 @FullMemoryWE()
-class DRTIOAuxControllerBare(Module):
+class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
     # Barebones version of the AuxController. No SRAM, no decoders.
     # add memories manually from tx and rx in target code.
     def get_tx_port(self):