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drtioaucontroller: made two decoders

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This commit is contained in:
mwojcik 2021-08-20 15:13:56 +02:00
parent e43684a3ed
commit b2d9003d9f
1 changed files with 8 additions and 4 deletions
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12
src/gateware/aux_controller.py
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@ -21,11 +21,15 @@ class DRTIOAuxControllerAxi(Module):
tx_sdram_if = SRAM(self.transmitter.mem, read_only=False) tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
rx_sdram_if = SRAM(self.receiver.mem, read_only=True) rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
wsb = log2_int(len(self.bus.w.data)//8) wsb = log2_int(len(self.bus.w.data)//8)
decoder = axi.AddressDecoder(self.bus, aw_decoder = axi.AddressDecoder(self.bus.aw,
[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus), [(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.aw),
(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)], (lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.aw)],
register=True) register=True)
self.submodules += tx_sdram_if, rx_sdram_if, decoder ar_decoder = axi.AddressDecoder(self.bus.ar,
[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.ar),
(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.ar)],
register=True)
self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
def get_csrs(self): def get_csrs(self):
return self.transmitter.get_csrs() + self.receiver.get_csrs() return self.transmitter.get_csrs() + self.receiver.get_csrs()