From b2d9003d9f93b5629562c097b93a8e90c9a1fab6 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Fri, 20 Aug 2021 15:13:56 +0200 Subject: [PATCH] drtioaucontroller: made two decoders --- src/gateware/aux_controller.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gateware/aux_controller.py b/src/gateware/aux_controller.py index 7b768fb8..c458e25a 100644 --- a/src/gateware/aux_controller.py +++ b/src/gateware/aux_controller.py @@ -21,11 +21,15 @@ class DRTIOAuxControllerAxi(Module): tx_sdram_if = SRAM(self.transmitter.mem, read_only=False) rx_sdram_if = SRAM(self.receiver.mem, read_only=True) wsb = log2_int(len(self.bus.w.data)//8) - decoder = axi.AddressDecoder(self.bus, - [(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus), - (lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)], + aw_decoder = axi.AddressDecoder(self.bus.aw, + [(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.aw), + (lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.aw)], register=True) - self.submodules += tx_sdram_if, rx_sdram_if, decoder + ar_decoder = axi.AddressDecoder(self.bus.ar, + [(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus.ar), + (lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus.ar)], + register=True) + self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder def get_csrs(self): return self.transmitter.get_csrs() + self.receiver.get_csrs()