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c336e450b1
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libboard_zynq/eth/phy: add PEF7071
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2020-09-29 16:01:54 +08:00 |
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273f9ea72b
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libboard_zynq/eth: fix comment
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2020-08-24 21:47:10 +08:00 |
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671968bac3
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libboard_zynq/eth: fixed tx lost packet
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2020-08-24 15:51:01 +08:00 |
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bb09d25378
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libboard_zynq/ethernet: ethernet fix and config
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2020-08-21 13:34:02 +08:00 |
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1a96a7550a
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libboard_zynq: make RegisterBlock constructors more consistent
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2020-08-13 14:49:26 +08:00 |
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36947104e3
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libboard_zynq: make constructor names more consistent
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2020-08-13 13:31:53 +08:00 |
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a36a82d86d
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reduce ethernet verbosity
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2020-08-04 22:15:01 +08:00 |
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1f05e6977e
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eth::phy: replace ExtendedStatus with PSSR
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2020-07-29 21:49:18 +02:00 |
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e408a8b22d
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eth::phy::extended_status: fix cap_1000base_x_full() bit position
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2020-07-29 21:29:28 +02:00 |
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27effb6257
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eth::phy: s/Marvel/Marvell/
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2020-07-29 20:08:38 +02:00 |
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de5f605d60
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eth: refactor peripheral instance into type parameter, improve clock setup
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2020-07-29 19:45:01 +02:00 |
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484e385160
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eth: implement DeviceCapabilities.max_burst_size
this is a hint that /could/ boost TCP performance.
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2020-07-16 00:17:13 +02:00 |
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b33ccf83ba
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eth: doc
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2020-06-18 18:07:50 +02:00 |
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a80a2c67ef
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eth: put desc list behind UncachedSlice, invalidate buffers, add barriers
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2020-06-18 01:28:29 +02:00 |
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a1a211334f
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eth: always just allocate desc list + buffers
buffers are allocated vec anyway. this removes the lifetime hack and
further prepares work on cache-line alignment to enable L1 writeback.
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2020-06-11 00:21:18 +02:00 |
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877f2c34bd
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libboard_zynq: use log logging
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2020-05-01 01:46:42 +02:00 |
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46af38906e
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libboard_zynq: wrap eth Buffer for alignment
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2020-03-29 00:08:43 +01:00 |
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aae85981e2
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libboard_zynq::clocks: setup clock sources and cpu clock
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2020-01-23 23:15:10 +01:00 |
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cf1983e543
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split into lib{register, cortex_a9, board_zynq, board_zc706} crates
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2019-12-17 23:35:58 +01:00 |
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