forked from M-Labs/zynq-rs
split into lib{register, cortex_a9, board_zynq, board_zc706} crates
This commit is contained in:
parent
1036ecc0f7
commit
cf1983e543
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@ -15,6 +15,53 @@ name = "byteorder"
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version = "1.3.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "libboard_zc706"
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version = "0.0.0"
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dependencies = [
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"libboard_zynq 0.0.0",
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"libcortex_a9 0.0.0",
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"libregister 0.0.0",
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"linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)",
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]
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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dependencies = [
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"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"libcortex_a9 0.0.0",
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"libregister 0.0.0",
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"linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)",
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"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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dependencies = [
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"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"libregister 0.0.0",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)",
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"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "libregister"
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version = "0.0.0"
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dependencies = [
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"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "linked_list_allocator"
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version = "0.6.4"
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@ -53,18 +100,6 @@ dependencies = [
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"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "zc706"
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version = "0.0.0"
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dependencies = [
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"bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"linked_list_allocator 0.6.4 (registry+https://github.com/rust-lang/crates.io-index)",
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"r0 0.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"smoltcp 0.5.0 (git+https://github.com/m-labs/smoltcp.git?rev=8eb01aca364aefe5f823d68d552d62c76c9be4a3)",
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"vcell 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"volatile-register 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[metadata]
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"checksum bit_field 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0"
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"checksum bitflags 1.1.0 (registry+https://github.com/rust-lang/crates.io-index)" = "3d155346769a6855b86399e9bc3814ab343cd3d62c7e985113d46a0ec3c281fd"
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25
Cargo.toml
25
Cargo.toml
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@ -1,8 +1,5 @@
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[package]
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name = "zc706"
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version = "0.0.0"
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authors = ["Astro <astro@spaceboyz.net>"]
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edition = "2018"
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[workspace]
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members = ["libregister", "libcortex_a9", "libboard_zynq", "libboard_zc706"]
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[profile.dev]
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panic = "abort"
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@ -13,21 +10,3 @@ panic = "abort"
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debug = true
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lto = true # Link-Time Optimization
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opt-level = 'z' # Optimize for size.
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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default = ["target_zc706"]
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[dependencies]
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r0 = "0.2"
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vcell = "0.1"
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volatile-register = "0.2"
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bit_field = "0.10"
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linked_list_allocator = { version = "0.6", default-features = false }
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[dependencies.smoltcp]
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git = "https://github.com/m-labs/smoltcp.git"
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rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
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features = ["ethernet", "proto-ipv4", "socket-tcp"]
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default-features = false
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@ -43,7 +43,7 @@ let
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zc706 = xbuildRustPackage {
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name = "zc706";
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src = ./.;
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cargoSha256 = "1k7b0bzkzhqggrmgzs7md7rrbid0b59a5l96ppr4rwxnh841vcdk";
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cargoSha256 = "15icqy72dck82czpsqz41yjsdar17vpi15v22j6z0zxhzf517rf7";
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nativeBuildInputs = [
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gcc
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];
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@ -0,0 +1,23 @@
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[package]
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name = "libboard_zc706"
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version = "0.0.0"
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authors = ["Astro <astro@spaceboyz.net>"]
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edition = "2018"
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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default = ["target_zc706"]
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[dependencies]
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r0 = "0.2"
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linked_list_allocator = { version = "0.6", default-features = false }
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libregister = { path = "../libregister" }
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libcortex_a9 = { path = "../libcortex_a9" }
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libboard_zynq = { path = "../libboard_zynq" }
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[dependencies.smoltcp]
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git = "https://github.com/m-labs/smoltcp.git"
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rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
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features = ["ethernet", "proto-ipv4", "socket-tcp"]
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default-features = false
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@ -1,4 +1,4 @@
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use crate::println;
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use libboard_zynq::println;
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#[no_mangle]
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pub unsafe extern "C" fn PrefetchAbort() {
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@ -1,8 +1,10 @@
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use r0::zero_bss;
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use vcell::VolatileCell;
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use crate::cortex_a9::{asm, regs::*, cache, mmu};
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use crate::zynq::{slcr, mpcore};
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use libregister::{
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VolatileCell,
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RegisterR, RegisterW, RegisterRW,
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};
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use libcortex_a9::{asm, regs::*, cache, mmu};
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use libboard_zynq::{slcr, mpcore};
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extern "C" {
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static mut __bss_start: u32;
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@ -81,7 +83,7 @@ unsafe fn boot_core1() -> ! {
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}
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fn l1_cache_init() {
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use crate::cortex_a9::cache::*;
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use libcortex_a9::cache::*;
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// Invalidate TLBs
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tlbiall();
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@ -1,9 +1,6 @@
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#![no_std]
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#![no_main]
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#![feature(asm)]
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#![feature(global_asm)]
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#![feature(naked_functions)]
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#![feature(never_type)]
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#![feature(alloc_error_handler)]
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#![feature(panic_info_message)]
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// TODO: disallow unused/dead_code when code moves into a lib crate
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@ -18,16 +15,13 @@ use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
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use smoltcp::time::Instant;
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use smoltcp::socket::SocketSet;
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use smoltcp::socket::{TcpSocket, TcpSocketBuffer};
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use libboard_zynq::{print, println, self as zynq};
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mod boot;
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mod regs;
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mod cortex_a9;
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mod abort;
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mod panic;
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mod zynq;
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mod stdio;
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mod ram;
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use cortex_a9::mutex::Mutex;
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use libcortex_a9::mutex::Mutex;
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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@ -36,8 +30,10 @@ static mut STACK_CORE1: [u32; 512] = [0; 512];
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pub fn main() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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use regs::RegisterR;
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println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
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{
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use libregister::RegisterR;
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println!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
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}
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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@ -110,7 +106,7 @@ pub fn main() {
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core1.stop();
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cortex_a9::asm::dsb();
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libcortex_a9::asm::dsb();
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print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32);
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for w in core1.stack {
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print!(" {:08X}", w);
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@ -1,4 +1,4 @@
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use crate::{print, println, zynq};
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use libboard_zynq::{slcr, print, println};
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#[panic_handler]
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fn panic(info: &core::panic::PanicInfo) -> ! {
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@ -14,6 +14,6 @@ fn panic(info: &core::panic::PanicInfo) -> ! {
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println!("");
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}
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zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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loop {}
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}
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@ -2,8 +2,8 @@ use core::alloc::GlobalAlloc;
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use core::ptr::NonNull;
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use alloc::alloc::Layout;
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use linked_list_allocator::Heap;
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use crate::cortex_a9::mutex::Mutex;
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use crate::zynq::ddr::DdrRam;
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use libcortex_a9::mutex::Mutex;
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use libboard_zynq::ddr::DdrRam;
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#[global_allocator]
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static ALLOCATOR: CortexA9Alloc = CortexA9Alloc(Mutex::new(Heap::empty()));
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@ -0,0 +1,25 @@
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[package]
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name = "libboard_zynq"
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version = "0.0.0"
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authors = ["Astro <astro@spaceboyz.net>"]
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edition = "2018"
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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default = ["target_zc706"]
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[dependencies]
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r0 = "0.2"
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vcell = "0.1"
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volatile-register = "0.2"
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bit_field = "0.10"
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linked_list_allocator = { version = "0.6", default-features = false }
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libregister = { path = "../libregister" }
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libcortex_a9 = { path = "../libcortex_a9" }
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[dependencies.smoltcp]
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git = "https://github.com/m-labs/smoltcp.git"
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rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
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features = ["ethernet", "proto-ipv4", "socket-tcp"]
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default-features = false
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@ -2,7 +2,7 @@
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use volatile_register::RW;
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use crate::{register, register_bit, register_bits};
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use libregister::{register, register_bit, register_bits};
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pub unsafe fn axi_hp0() -> &'static RegisterBlock {
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&*(0xF8008000 as *const _)
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@ -1,4 +1,4 @@
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use super::slcr;
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#[cfg(feature = "target_zc706")]
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@ -1,4 +1,4 @@
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use crate::{print, println};
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use super::slcr;
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use super::clocks::CpuClocks;
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@ -1,7 +1,8 @@
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use volatile_register::{RO, RW};
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use crate::{register, register_bit, register_bits_typed};
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use libregister::{register, register_bit, register_bits_typed};
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#[allow(unused)]
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#[repr(u8)]
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pub enum DataBusWidth {
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Width32bit = 0b00,
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@ -1,4 +1,4 @@
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use crate::regs::*;
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use libregister::*;
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use crate::println;
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use super::slcr;
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use super::clocks::CpuClocks;
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_bits_typed};
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use libregister::{register, register_bit, register_bits, register_bits_typed};
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#[repr(C)]
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pub struct RegisterBlock {
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@ -1,6 +1,5 @@
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use core::ops::Deref;
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use vcell::VolatileCell;
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use crate::{register, register_bit, register_bits, regs::*};
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use libregister::*;
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use super::MTU;
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#[derive(Debug)]
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@ -1,6 +1,5 @@
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use core::ops::{Deref, DerefMut};
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use vcell::VolatileCell;
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use crate::{register, register_bit, register_bits, regs::*};
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use libregister::*;
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use super::{MTU, regs};
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/// Descriptor entry
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@ -2,7 +2,7 @@
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use crate::{print, println};
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use core::marker::PhantomData;
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use super::slcr;
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use super::clocks::CpuClocks;
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|
|
@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits};
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use libregister::{register, register_bit, register_bits};
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#[repr(C)]
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pub struct RegisterBlock {
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@ -26,6 +26,7 @@ macro_rules! u8_register {
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}
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impl $name {
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#[allow(unused)]
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pub fn is_zeroed(&self) -> bool {
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self.inner == 0
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}
|
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@ -1,4 +1,4 @@
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use super::regs;
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use super::{SpiWord, Flash, Manual};
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|
|
@ -1,6 +1,9 @@
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#![no_std]
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pub mod slcr;
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pub mod clocks;
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pub mod uart;
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pub mod stdio;
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pub mod eth;
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pub mod axi_hp;
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pub mod axi_gp;
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@ -1,8 +1,10 @@
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///! Register definitions for Application Processing Unit (mpcore)
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use volatile_register::{RO, RW};
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use crate::{register, register_at, register_bit, register_bits,
|
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regs::RegisterW, regs::RegisterRW};
|
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use libregister::{
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register, register_at, register_bit, register_bits,
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RegisterW, RegisterRW,
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};
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|
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#[repr(C)]
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pub struct RegisterBlock {
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@ -1,9 +1,11 @@
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///! Register definitions for System Level Control
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|
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use volatile_register::{RO, RW};
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use crate::{register, register_at,
|
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register_bit, register_bits, register_bits_typed,
|
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regs::RegisterW, regs::RegisterRW};
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use libregister::{
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register, register_at,
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register_bit, register_bits, register_bits_typed,
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RegisterW, RegisterRW,
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};
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|
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#[repr(u8)]
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pub enum PllSource {
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|
@ -1,6 +1,6 @@
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use core::ops::{Deref, DerefMut};
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use crate::cortex_a9::mutex::{Mutex, MutexGuard};
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use crate::zynq::uart::Uart;
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use libcortex_a9::mutex::{Mutex, MutexGuard};
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use crate::uart::Uart;
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const UART_RATE: u32 = 115_200;
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static mut UART: Mutex<LazyUart> = Mutex::new(LazyUart::Uninitialized);
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|
@ -47,7 +47,7 @@ impl DerefMut for LazyUart {
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macro_rules! print {
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($($arg:tt)*) => ({
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use core::fmt::Write;
|
||||
let mut uart = crate::stdio::get_uart();
|
||||
let mut uart = $crate::stdio::get_uart();
|
||||
let _ = write!(uart, $($arg)*);
|
||||
})
|
||||
}
|
||||
|
@ -56,7 +56,7 @@ macro_rules! print {
|
|||
macro_rules! println {
|
||||
($($arg:tt)*) => ({
|
||||
use core::fmt::Write;
|
||||
let mut uart = crate::stdio::get_uart();
|
||||
let mut uart = $crate::stdio::get_uart();
|
||||
let _ = write!(uart, $($arg)*);
|
||||
let _ = write!(uart, "\r\n");
|
||||
while !uart.tx_fifo_empty() {}
|
|
@ -1,4 +1,4 @@
|
|||
use crate::regs::*;
|
||||
use libregister::*;
|
||||
use super::regs::{RegisterBlock, BaudRateGen, BaudRateDiv};
|
||||
|
||||
const BDIV_MIN: u32 = 4;
|
|
@ -1,6 +1,6 @@
|
|||
use core::fmt;
|
||||
|
||||
use crate::regs::*;
|
||||
use libregister::*;
|
||||
use super::slcr;
|
||||
use super::clocks::CpuClocks;
|
||||
|
|
@ -1,7 +1,11 @@
|
|||
use volatile_register::{RO, WO, RW};
|
||||
|
||||
use crate::{register, register_bit, register_bits, register_bits_typed, register_at};
|
||||
use libregister::{
|
||||
register, register_at,
|
||||
register_bit, register_bits, register_bits_typed,
|
||||
};
|
||||
|
||||
#[allow(unused)]
|
||||
#[repr(u8)]
|
||||
pub enum ChannelMode {
|
||||
Normal = 0b00,
|
||||
|
@ -10,6 +14,7 @@ pub enum ChannelMode {
|
|||
RemoteLoopback = 0b11,
|
||||
}
|
||||
|
||||
#[allow(unused)]
|
||||
#[repr(u8)]
|
||||
pub enum ParityMode {
|
||||
EvenParity = 0b000,
|
||||
|
@ -19,6 +24,7 @@ pub enum ParityMode {
|
|||
None = 0b100,
|
||||
}
|
||||
|
||||
#[allow(unused)]
|
||||
#[repr(u8)]
|
||||
pub enum StopBits {
|
||||
One = 0b00,
|
|
@ -0,0 +1,23 @@
|
|||
[package]
|
||||
name = "libcortex_a9"
|
||||
version = "0.0.0"
|
||||
authors = ["Astro <astro@spaceboyz.net>"]
|
||||
edition = "2018"
|
||||
|
||||
[features]
|
||||
target_zc706 = []
|
||||
target_cora_z7_10 = []
|
||||
default = ["target_zc706"]
|
||||
|
||||
[dependencies]
|
||||
r0 = "0.2"
|
||||
vcell = "0.1"
|
||||
volatile-register = "0.2"
|
||||
bit_field = "0.10"
|
||||
libregister = { path = "../libregister" }
|
||||
|
||||
[dependencies.smoltcp]
|
||||
git = "https://github.com/m-labs/smoltcp.git"
|
||||
rev = "8eb01aca364aefe5f823d68d552d62c76c9be4a3"
|
||||
features = ["ethernet", "proto-ipv4", "socket-tcp"]
|
||||
default-features = false
|
|
@ -1,3 +1,7 @@
|
|||
#![no_std]
|
||||
#![feature(asm, global_asm)]
|
||||
#![feature(never_type)]
|
||||
|
||||
pub mod asm;
|
||||
pub mod regs;
|
||||
pub mod cache;
|
|
@ -1,6 +1,6 @@
|
|||
use bit_field::BitField;
|
||||
use super::{regs::*, asm};
|
||||
use crate::regs::RegisterW;
|
||||
use libregister::RegisterW;
|
||||
|
||||
#[derive(Copy, Clone)]
|
||||
#[repr(u8)]
|
|
@ -1,5 +1,7 @@
|
|||
use crate::{register_bit, register_bits};
|
||||
use crate::regs::{RegisterR, RegisterW, RegisterRW};
|
||||
use libregister::{
|
||||
register_bit, register_bits,
|
||||
RegisterR, RegisterW, RegisterRW,
|
||||
};
|
||||
|
||||
macro_rules! def_reg_r {
|
||||
($name:tt, $type: ty, $asm_instr:tt) => {
|
|
@ -0,0 +1,10 @@
|
|||
[package]
|
||||
name = "libregister"
|
||||
version = "0.0.0"
|
||||
authors = ["Astro <astro@spaceboyz.net>"]
|
||||
edition = "2018"
|
||||
|
||||
[dependencies]
|
||||
vcell = "0.1"
|
||||
volatile-register = "0.2"
|
||||
bit_field = "0.10"
|
|
@ -1,10 +1,11 @@
|
|||
//! Type-safe interface to peripheral registers akin to the code that
|
||||
//! svd2rust generates.
|
||||
#![allow(unused)]
|
||||
|
||||
use vcell::VolatileCell;
|
||||
use volatile_register::{RO, WO, RW};
|
||||
use bit_field::BitField;
|
||||
#![no_std]
|
||||
|
||||
pub use vcell::VolatileCell;
|
||||
pub use volatile_register::{RO, WO, RW};
|
||||
pub use bit_field::BitField;
|
||||
|
||||
/// A readable register
|
||||
pub trait RegisterR {
|
||||
|
@ -51,7 +52,7 @@ macro_rules! register_common {
|
|||
#[macro_export]
|
||||
macro_rules! register_r {
|
||||
($mod_name: ident, $struct_name: ident) => (
|
||||
impl crate::regs::RegisterR for $struct_name {
|
||||
impl libregister::RegisterR for $struct_name {
|
||||
type R = $mod_name::Read;
|
||||
|
||||
fn read(&self) -> Self::R {
|
||||
|
@ -65,7 +66,7 @@ macro_rules! register_r {
|
|||
#[macro_export]
|
||||
macro_rules! register_w {
|
||||
($mod_name: ident, $struct_name: ident) => (
|
||||
impl crate::regs::RegisterW for $struct_name {
|
||||
impl libregister::RegisterW for $struct_name {
|
||||
type W = $mod_name::Write;
|
||||
|
||||
fn zeroed() -> $mod_name::Write {
|
||||
|
@ -84,7 +85,7 @@ macro_rules! register_w {
|
|||
#[macro_export]
|
||||
macro_rules! register_rw {
|
||||
($mod_name: ident, $struct_name: ident) => (
|
||||
impl crate::regs::RegisterRW for $struct_name {
|
||||
impl libregister::RegisterRW for $struct_name {
|
||||
fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
|
||||
unsafe {
|
||||
self.inner.modify(|inner| {
|
||||
|
@ -101,7 +102,7 @@ macro_rules! register_rw {
|
|||
#[macro_export]
|
||||
macro_rules! register_vcell {
|
||||
($mod_name: ident, $struct_name: ident) => (
|
||||
impl crate::regs::RegisterR for $struct_name {
|
||||
impl libregister::RegisterR for $struct_name {
|
||||
type R = $mod_name::Read;
|
||||
|
||||
fn read(&self) -> Self::R {
|
||||
|
@ -109,7 +110,7 @@ macro_rules! register_vcell {
|
|||
$mod_name::Read { inner }
|
||||
}
|
||||
}
|
||||
impl crate::regs::RegisterW for $struct_name {
|
||||
impl libregister::RegisterW for $struct_name {
|
||||
type W = $mod_name::Write;
|
||||
|
||||
fn zeroed() -> $mod_name::Write {
|
||||
|
@ -120,7 +121,7 @@ macro_rules! register_vcell {
|
|||
self.inner.set(w.inner);
|
||||
}
|
||||
}
|
||||
impl crate::regs::RegisterRW for $struct_name {
|
||||
impl libregister::RegisterRW for $struct_name {
|
||||
fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&mut self, f: F) {
|
||||
let r = self.read();
|
||||
let w = $mod_name::Write { inner: r.inner };
|
||||
|
@ -136,28 +137,28 @@ macro_rules! register_vcell {
|
|||
macro_rules! register {
|
||||
// Define read-only register
|
||||
($mod_name: ident, $struct_name: ident, RO, $inner: ty) => (
|
||||
crate::register_common!($mod_name, $struct_name, volatile_register::RO<$inner>, $inner);
|
||||
crate::register_r!($mod_name, $struct_name);
|
||||
libregister::register_common!($mod_name, $struct_name, libregister::RO<$inner>, $inner);
|
||||
libregister::register_r!($mod_name, $struct_name);
|
||||
);
|
||||
|
||||
// Define write-only register
|
||||
($mod_name: ident, $struct_name: ident, WO, $inner: ty) => (
|
||||
crate::register_common!($mod_name, $struct_name, volatile_register::WO<$inner>, $inner);
|
||||
crate::register_w!($mod_name, $struct_name);
|
||||
libregister::register_common!($mod_name, $struct_name, volatile_register::WO<$inner>, $inner);
|
||||
libregister::register_w!($mod_name, $struct_name);
|
||||
);
|
||||
|
||||
// Define read-write register
|
||||
($mod_name: ident, $struct_name: ident, RW, $inner: ty) => (
|
||||
crate::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner);
|
||||
crate::register_r!($mod_name, $struct_name);
|
||||
crate::register_w!($mod_name, $struct_name);
|
||||
crate::register_rw!($mod_name, $struct_name);
|
||||
libregister::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner);
|
||||
libregister::register_r!($mod_name, $struct_name);
|
||||
libregister::register_w!($mod_name, $struct_name);
|
||||
libregister::register_rw!($mod_name, $struct_name);
|
||||
);
|
||||
|
||||
// Define read-write register
|
||||
($mod_name: ident, $struct_name: ident, VolatileCell, $inner: ty) => (
|
||||
crate::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner);
|
||||
crate::register_vcell!($mod_name, $struct_name);
|
||||
libregister::register_common!($mod_name, $struct_name, VolatileCell<$inner>, $inner);
|
||||
libregister::register_vcell!($mod_name, $struct_name);
|
||||
);
|
||||
}
|
||||
|
Loading…
Reference in New Issue