15 Commits

Author	SHA1	Message	Date
mwojcik	072fd5f015	eth phy: set LEDs only on Kasli-SoC	2022-03-10 16:42:25 +08:00
mwojcik	2b3c7e4b2f	eth leds: ... * break led0 from led1 - similar, but not the same settings (led2 not implemented) * fix values, make it compilable * set default behavior (one led for link, other for activity)	2022-03-10 16:42:25 +08:00
Astro	ddff295ae1	libboard_zynq: implement eth hot-plugging	2020-11-20 17:12:22 +01:00
pca006132	bb09d25378	libboard_zynq/ethernet: ethernet fix and config	2020-08-21 13:34:02 +08:00
Harry Ho	36947104e3	libboard_zynq: make constructor names more consistent	2020-08-13 13:31:53 +08:00
Sebastien Bourdeauducq	a36a82d86d	reduce ethernet verbosity	2020-08-04 22:15:01 +08:00
Astro	1f05e6977e	eth::phy: replace ExtendedStatus with PSSR	2020-07-29 21:49:18 +02:00
Astro	de5f605d60	eth: refactor peripheral instance into type parameter, improve clock setup	2020-07-29 19:45:01 +02:00
Astro	484e385160	eth: implement DeviceCapabilities.max_burst_size ... this is a hint that /could/ boost TCP performance.	2020-07-16 00:17:13 +02:00
Astro	a80a2c67ef	eth: put desc list behind UncachedSlice, invalidate buffers, add barriers	2020-06-18 01:28:29 +02:00
Astro	a1a211334f	eth: always just allocate desc list + buffers ... buffers are allocated vec anyway. this removes the lifetime hack and further prepares work on cache-line alignment to enable L1 writeback.	2020-06-11 00:21:18 +02:00
Astro	877f2c34bd	libboard_zynq: use log logging	2020-05-01 01:46:42 +02:00
Astro	46af38906e	libboard_zynq: wrap eth Buffer for alignment	2020-03-29 00:08:43 +01:00
Astro	aae85981e2	libboard_zynq::clocks: setup clock sources and cpu clock	2020-01-23 23:15:10 +01:00
Astro	cf1983e543	split into lib{register, cortex_a9, board_zynq, board_zc706} crates	2019-12-17 23:35:58 +01:00