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5c62716a99
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zynq::eth: switch rx and tx descriptor words to vcell
vcell can be initialized cleanly.
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2019-10-31 03:15:13 +01:00 |
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a8886de067
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zynq::ddr: implement configure_iob()
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2019-10-24 01:24:12 +02:00 |
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6bf210366a
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regs: properly emit doc_comments
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2019-05-24 23:49:49 +02:00 |
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179c617904
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add register_bits_typed! macro
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2019-05-23 18:29:05 +02:00 |
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785e726661
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RegisterW/RegisterRW: required &mut self for safety
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2019-05-23 18:01:18 +02:00 |
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5d02fe5c95
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slcr: with_slcr() for unlock/lock
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2019-05-21 01:30:17 +02:00 |
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351d18c10f
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add register_at! macro
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2019-05-20 23:01:50 +02:00 |
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7872e00182
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uart: move logic outside regs
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2019-05-07 17:46:37 +02:00 |
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ca9b10dce8
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refactor regs macros for RO/WO/RW access
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2019-05-07 00:32:45 +02:00 |
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1e540a1175
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replace #[repr(packed)] with #[repr(C)]
avoids warnings regarding unsafe behaviour
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2019-05-07 00:05:38 +02:00 |
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55957eea09
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regs macros
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2019-05-06 23:56:53 +02:00 |
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