forked from M-Labs/zynq-rs
refactor regs macros for RO/WO/RW access
This commit is contained in:
parent
1e540a1175
commit
ca9b10dce8
89
src/regs.rs
89
src/regs.rs
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@ -1,24 +1,37 @@
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//! Interface to peripheral registers akin to the code that svd2rust
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//! generates.
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#![allow(unused)]
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use volatile_register::{RO, WO, RW};
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use bit_field::BitField;
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pub trait Register {
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/// A readable register
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pub trait RegisterR {
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/// Type-safe reader for the register value
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type R;
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type W;
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fn read(&self) -> Self::R;
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}
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/// A writable register
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pub trait RegisterW {
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/// Type-safe writer to the register value
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type W;
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fn zeroed() -> Self::W;
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fn write(&self, w: Self::W);
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fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&self, f: F);
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}
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/// A modifiable register
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pub trait RegisterRW: RegisterR + RegisterW {
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fn modify<F: FnOnce(<Self as RegisterR>::R, <Self as RegisterW>::W) -> <Self as RegisterW>::W>(&self, f: F);
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! register {
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($mod_name: ident, $struct_name: ident, $inner: ty) => (
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macro_rules! register_common {
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($mod_name: ident, $struct_name: ident, $access: ty, $inner: ty) => (
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#[repr(C)]
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pub struct $struct_name {
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inner: RW<$inner>,
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inner: $access,
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}
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pub mod $mod_name {
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@ -29,28 +42,46 @@ macro_rules! register {
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pub inner: $inner,
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}
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}
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impl $struct_name {
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pub fn zeroed() -> $mod_name::Write {
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$mod_name::Write { inner: 0 }
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}
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}
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impl crate::regs::Register for $struct_name {
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);
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! register_r {
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($mod_name: ident, $struct_name: ident) => (
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impl crate::regs::RegisterR for $struct_name {
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type R = $mod_name::Read;
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type W = $mod_name::Write;
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fn read(&self) -> Self::R {
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let inner = self.inner.read();
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$mod_name::Read { inner }
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}
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}
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);
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! register_w {
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($mod_name: ident, $struct_name: ident) => (
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impl crate::regs::RegisterW for $struct_name {
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type W = $mod_name::Write;
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fn zeroed() -> $mod_name::Write {
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$mod_name::Write { inner: 0 }
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}
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fn write(&self, w: Self::W) {
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unsafe {
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self.inner.write(w.inner);
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}
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}
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}
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);
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}
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#[doc(hidden)]
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#[macro_export]
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macro_rules! register_rw {
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($mod_name: ident, $struct_name: ident) => (
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impl crate::regs::RegisterRW for $struct_name {
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fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&self, f: F) {
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unsafe {
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self.inner.modify(|inner| {
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@ -63,6 +94,31 @@ macro_rules! register {
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);
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}
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/// Main macro for register definition
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#[macro_export]
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macro_rules! register {
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// Define read-only register
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($mod_name: ident, $struct_name: ident, RO, $inner: ty) => (
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crate::register_common!($mod_name, $struct_name, volatile_register::RO<$inner>, $inner);
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crate::register_r!($mod_name, $struct_name);
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);
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// Define write-only register
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($mod_name: ident, $struct_name: ident, WO, $inner: ty) => (
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crate::register_common!($mod_name, $struct_name, volatile_register::WO<$inner>, $inner);
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crate::register_w!($mod_name, $struct_name);
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);
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// Define read-write register
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($mod_name: ident, $struct_name: ident, RW, $inner: ty) => (
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crate::register_common!($mod_name, $struct_name, volatile_register::RW<$inner>, $inner);
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crate::register_r!($mod_name, $struct_name);
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crate::register_w!($mod_name, $struct_name);
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crate::register_rw!($mod_name, $struct_name);
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);
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}
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/// Define a 1-bit field of a register
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#[macro_export]
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macro_rules! register_bit {
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($mod_name: ident, $name: ident, $bit: expr) => (
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@ -85,6 +141,7 @@ macro_rules! register_bit {
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);
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}
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/// Define a multi-bit field of a register
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#[macro_export]
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macro_rules! register_bits {
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($mod_name: ident, $name: ident, $type: ty, $bit_begin: expr, $bit_end: expr) => (
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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#[allow(unused)]
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use crate::{register, register_bit, register_bits, regs::Register};
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use crate::{register, register_bit, register_bits, regs::RegisterRW};
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pub enum PllSource {
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IoPll = 0b00,
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@ -8,7 +8,7 @@ pub enum PllSource {
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DdrPll = 0b11,
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}
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register!(uart_clk_ctrl, UartClkCtrl, u32);
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register!(uart_clk_ctrl, UartClkCtrl, RW, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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@ -32,7 +32,7 @@ impl UartClkCtrl {
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}
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}
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register!(uart_rst_ctrl, UartRstCtrl, u32);
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register!(uart_rst_ctrl, UartRstCtrl, RW, u32);
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register_bit!(uart_rst_ctrl, uart0_ref_rst, 3);
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register_bit!(uart_rst_ctrl, uart1_ref_rst, 2);
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register_bit!(uart_rst_ctrl, uart0_cpu1x_rst, 1);
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@ -1,3 +1,5 @@
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#![allow(unused)]
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mod regs;
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pub use regs::RegisterBlock;
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@ -25,10 +27,8 @@ impl Uart {
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}
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pub fn write_byte(&self, v: u8) {
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unsafe {
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while self.regs.tx_fifo_full() {}
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while self.regs.tx_fifo_full() {}
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self.regs.write_byte(v);
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}
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self.regs.write_byte(v);
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}
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}
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@ -1,7 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use bit_field::BitField;
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use crate::{register, register_bit, register_bits, regs::Register};
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use crate::{register, register_bit, register_bits, regs::*};
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#[repr(u8)]
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pub enum ParityMode {
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@ -33,7 +32,7 @@ pub struct RegisterBlock {
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tx_fifo_trigger_level: RW<u32>,
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}
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register!(control, Control, u32);
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register!(control, Control, RW, u32);
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register_bit!(control, rxrst, 0);
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register_bit!(control, txrst, 1);
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register_bit!(control, rxen, 2);
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@ -41,19 +40,19 @@ register_bit!(control, rxdis, 3);
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register_bit!(control, txen, 4);
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register_bit!(control, txdis, 5);
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register!(mode, Mode, u32);
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register!(mode, Mode, RW, u32);
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register_bits!(mode, par, u8, 3, 5);
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register!(baud_rate_gen, BaudRateGen, u32);
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register!(baud_rate_gen, BaudRateGen, RW, u32);
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register_bits!(baud_rate_gen, cd, u16, 0, 15);
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register!(channel_sts, ChannelSts, u32);
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register!(channel_sts, ChannelSts, RO, u32);
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register_bit!(channel_sts, txfull, 4);
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register!(tx_rx_fifo, TxRxFifo, u32);
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register!(tx_rx_fifo, TxRxFifo, RW, u32);
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register_bits!(tx_rx_fifo, data, u32, 0, 31);
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register!(baud_rate_div, BaudRateDiv, u32);
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register!(baud_rate_div, BaudRateDiv, RW, u32);
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register_bits!(baud_rate_div, bdiv, u8, 0, 7);
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impl RegisterBlock {
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