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47ec0116a9
|
use uart1 with more configuration
|
2019-05-21 01:30:54 +02:00 |
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5d02fe5c95
|
slcr: with_slcr() for unlock/lock
|
2019-05-21 01:30:17 +02:00 |
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351d18c10f
|
add register_at! macro
|
2019-05-20 23:01:50 +02:00 |
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c88374eab1
|
fix SP init
|
2019-05-20 01:21:22 +02:00 |
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b754581452
|
eth: add regs and init
|
2019-05-07 19:28:33 +02:00 |
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7872e00182
|
uart: move logic outside regs
|
2019-05-07 17:46:37 +02:00 |
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275f297309
|
uart: impl fmt::Write
|
2019-05-07 16:45:31 +02:00 |
|
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ca9b10dce8
|
refactor regs macros for RO/WO/RW access
|
2019-05-07 00:32:45 +02:00 |
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1e540a1175
|
replace #[repr(packed)] with #[repr(C)]
avoids warnings regarding unsafe behaviour
|
2019-05-07 00:05:38 +02:00 |
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fdc6c38de6
|
enable_uart0(): add srcsel
|
2019-05-07 00:01:43 +02:00 |
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55957eea09
|
regs macros
|
2019-05-06 23:56:53 +02:00 |
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9b414e2408
|
PoC: boot, uart output in qemu
|
2019-05-05 14:56:23 +02:00 |
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