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srenblad
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zynq-rs
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2.1
MiB
7e12468bf2
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5 Commits
Author
SHA1
Message
Date
Astro
7872e00182
uart: move logic outside regs
2019-05-07 17:46:37 +02:00
Astro
ca9b10dce8
refactor regs macros for RO/WO/RW access
2019-05-07 00:32:45 +02:00
Astro
1e540a1175
replace #[repr(packed)] with #[repr(C)]
...
avoids warnings regarding unsafe behaviour
2019-05-07 00:05:38 +02:00
Astro
55957eea09
regs macros
2019-05-06 23:56:53 +02:00
Astro
9b414e2408
PoC: boot, uart output in qemu
2019-05-05 14:56:23 +02:00