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27114aec62
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zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage
this seems to make DDR RAM work.
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2019-10-27 20:30:56 +01:00 |
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9b4f07f37c
|
zynq::ddr, main: parameters, memtest
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2019-10-25 23:19:34 +02:00 |
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|
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e61d1268ac
|
zynq::slcr: doc, fix
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2019-10-25 23:18:18 +02:00 |
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|
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a4d3360a70
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zynq::slcr: implement Display for PllStatus
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2019-10-25 20:38:10 +02:00 |
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838434cdec
|
zynq::ddr: wait for init
|
2019-10-25 19:15:22 +02:00 |
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|
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4cf5283ba8
|
zynq::ddr: implement reset_ddrc(), add to main
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2019-10-24 01:39:14 +02:00 |
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a8886de067
|
zynq::ddr: implement configure_iob()
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2019-10-24 01:24:12 +02:00 |
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afda48e3fe
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zynq::ddr: add clock_setup(), calibrate_iob_impedance()
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2019-10-22 01:25:35 +02:00 |
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c046bbf8a2
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move slcr, clocks, uart, eth into src/zynq/
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2019-10-21 22:19:03 +02:00 |
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9d725bcf0f
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zynq::ddr: init with clock setup
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2019-10-21 22:12:10 +02:00 |
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58cf9833cc
|
slcr: implement PllCfg and DdrClkCtrl
|
2019-10-21 22:10:51 +02:00 |
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83b8bb096a
|
add zynq::axi_gp
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2019-10-19 01:46:43 +02:00 |
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b541160f38
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add zynq::axi_hp
|
2019-10-18 23:46:00 +02:00 |
|
Björn Stein
|
1804c4c6e8
|
cortex_a9: add proper L1 cache invalidation
|
2019-10-18 00:11:51 +02:00 |
|
Björn Stein
|
d87b874b21
|
eth: add memory barriers, reorder access
|
2019-10-18 00:04:22 +02:00 |
|
Björn Stein
|
9053166acc
|
eth: increase desc list safety
|
2019-10-18 00:03:17 +02:00 |
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4e9c38527e
|
rm debug, delint
|
2019-09-29 03:01:24 +02:00 |
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a76214cb9d
|
eth: split into Eth and EthInner
|
2019-09-29 02:58:17 +02:00 |
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0f6bc68d1f
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eth: prepare link change detection
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2019-09-29 02:30:03 +02:00 |
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378755a0ce
|
main: bump RX_LEN/TX_LEN to 2
|
2019-09-29 01:40:38 +02:00 |
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|
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644cc64524
|
eth: align DescEntries
|
2019-09-29 01:39:12 +02:00 |
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|
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f9cc561144
|
link.x: fix __stack_start
This fixes the memory corruption problem.
|
2019-09-29 01:38:47 +02:00 |
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|
|
06bc7ba809
|
openocd: fix PL_TAPID for both targets
Fixes Gitea issue #1
|
2019-09-28 23:53:40 +02:00 |
|
|
|
d5334cc083
|
default.nix: fix use of rustManifest
part of Gitea issue #4
|
2019-09-26 23:34:06 +02:00 |
|
|
|
20249cf2da
|
default.nix: build zc706
|
2019-09-26 17:54:37 +02:00 |
|
|
|
ace24112fa
|
Cargo.toml: use compiler_builtins release
|
2019-09-26 17:54:05 +02:00 |
|
|
|
109a203e02
|
default.nix: add a static channel-rust-nightly.toml that fits the current rustcSrc
part of Gitea issue #4
|
2019-09-26 17:17:31 +02:00 |
|
|
|
5ef0213b97
|
default.nix: update rustcSrc
rev of 2019-09-26 doesn't fit today's nightly build.
|
2019-09-26 17:14:58 +02:00 |
|
|
|
d210b2b13f
|
shell.nix: use gcc cross pkg that actually builds
|
2019-09-26 16:24:47 +02:00 |
|
|
|
c38b2e418e
|
shell.nix: add openocd and gdb
|
2019-08-30 16:14:23 +08:00 |
|
|
|
6771531255
|
README: fix openocd not finding files
|
2019-08-20 13:45:50 +08:00 |
|
|
|
4c62ce0dad
|
main: restrict eth buffers to 1 each
|
2019-08-19 02:21:36 +02:00 |
|
|
|
9c73cf130d
|
eth: wait for link
|
2019-08-19 02:21:02 +02:00 |
|
|
|
c5a7f059c2
|
linker script: fix default ocm memory regions
|
2019-08-19 02:19:48 +02:00 |
|
|
|
cc0c4e521e
|
linker script: shrink STACK_SIZE to avoid DataAborts
|
2019-08-19 01:18:12 +02:00 |
|
|
|
45ed5f6c5b
|
abort handlers: replace panic with infinite loop
|
2019-08-19 01:18:12 +02:00 |
|
|
|
d11e581862
|
main: setup smoltcp
still panics, leading to a DataAbort
|
2019-08-19 01:18:12 +02:00 |
|
|
|
3a5ed0aac6
|
eth: add smoltcp support
|
2019-08-19 01:18:12 +02:00 |
|
|
|
5603766c5d
|
eth: enable csum offloading
should prevent FCS errors
|
2019-08-19 01:12:52 +02:00 |
|
|
|
43c3f3e4a6
|
eth: fix tx_clock magnitude bug
Ethernet TX now works!
|
2019-08-18 22:52:05 +02:00 |
|
|
|
4bc1d21ae9
|
eth: rm obsolete TODO
|
2019-08-18 22:44:33 +02:00 |
|
|
|
bfb3a00a4e
|
eth: derive proper mdc_clk_div from clocks
|
2019-08-18 22:43:56 +02:00 |
|
|
|
022da2a7a7
|
default.nix: update rustcSrc
didn't fit with rust-nightly any more
|
2019-08-18 22:16:47 +02:00 |
|
|
|
b8818863c4
|
read clocks
|
2019-08-17 03:20:04 +02:00 |
|
|
|
1f9ad5ff62
|
delint
|
2019-08-11 00:56:54 +02:00 |
|
|
|
e135b27c13
|
openocd: fix PL_TAPID for both zc706 and cora-z7-10
|
2019-08-10 20:59:07 +02:00 |
|
|
|
80e808208e
|
README: update to cargo-xbuild
|
2019-08-08 18:19:47 +02:00 |
|
|
|
b7690c9702
|
fix UART_REF_CLK
started to become garbled.
|
2019-08-07 00:27:01 +02:00 |
|
|
|
66c3470afd
|
link.x: rm unneeded ALIGN(4)
|
2019-08-07 00:26:46 +02:00 |
|
|
|
d001593a36
|
rm bcmp
|
2019-08-06 22:03:23 +02:00 |
|
