forked from M-Labs/zynq-rs
eth: derive proper mdc_clk_div from clocks
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@ -10,6 +10,8 @@ pub mod tx;
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/// Size of all the buffers
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pub const MTU: usize = 1536;
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/// Maximum MDC clock
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const MAX_MDC: u32 = 2_500_000;
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pub struct Eth<RX, TX> {
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regs: &'static mut regs::RegisterBlock,
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@ -288,6 +290,9 @@ impl<RX, TX> Eth<RX, TX> {
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}
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fn configure(&mut self, macaddr: [u8; 6]) {
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let clocks = CpuClocks::get();
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let mut mdc_clk_div = (clocks.cpu_1x() / MAX_MDC) + 1;
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self.regs.net_cfg.write(
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regs::NetCfg::zeroed()
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.full_duplex(true)
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@ -301,7 +306,7 @@ impl<RX, TX> Eth<RX, TX> {
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.fcs_remove(true)
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// One of the slower speeds
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// TODO: calculate properly
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.mdc_clk_div(0b110)
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.mdc_clk_div((mdc_clk_div >> 4).min(0b111) as u8)
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);
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let macaddr_msbs =
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