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zynq-rs
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665 Commits

Author SHA1 Message Date
Astro 0aa75d3544 experiments: fix timer.get_us() usage 2020-07-22 23:47:57 +02:00
Astro f36b1a610e timer::global: wrap us in Microseconds, impl embedded_hal blocking delay traits 2020-07-22 23:41:15 +02:00
Astro 7f45d10af3 timer::global::CountDown: fix delaying from "up to" to "at least" the timespan 2020-07-22 22:43:10 +02:00
Astro 855d94c48e dmac: remove unused module 2020-07-20 19:42:32 +02:00
Sebastien Bourdeauducq 84f1380f48 libasync: assert that callback consumes data in smoltcp recv 2020-07-19 16:14:29 +08:00
Sebastien Bourdeauducq f8785c3f07 fix some compilation warnings 2020-07-19 15:39:08 +08:00
Sebastien Bourdeauducq 7b78bc0494 libasync: new stream.recv API 
M-Labs/artiq-zynq#40 (comment)
 2020-07-19 15:34:32 +08:00
Sebastien Bourdeauducq ef88a1313a shell.nix: remove gcc 2020-07-19 15:34:18 +08:00
Astro 484e385160 eth: implement DeviceCapabilities.max_burst_size 
this is a hint that /could/ boost TCP performance.
 2020-07-16 00:17:13 +02:00
pca006132 074438c3c7 libcortex_a9: added `try_lock` for mutex. 2020-07-15 16:44:01 +08:00
Astro 191abf6b8f mpidr: wrap with proper bitfield getters 
Prevents callers from dealing with CORE_MASK.
 2020-07-08 00:04:54 +02:00
Sebastien Bourdeauducq 371e59cef5 libboard_zynq: add fpgax_clk_ctrl registers 2020-07-07 19:37:51 +08:00
pca006132 e67efe439b libsupport: fixed core1 restart. 
The TRM mentioned that user should stop the clock, de-assert the reset,
and then restart the clock for core reset.

This fixes the kernel restart problem in one of the zc706 board.
 2020-07-07 10:17:15 +08:00
Astro e4e7141bf3 ddr: delint 2020-07-06 19:46:18 +02:00
Sebastien Bourdeauducq f68b5896ce remove unused imports 2020-07-06 21:03:36 +08:00
Sebastien Bourdeauducq e430600683 fix exception vectors 2020-07-06 21:02:46 +08:00
Sebastien Bourdeauducq 0c60d684e4 slcr: remove soft reset 
Does not work and probably difficult to get to work.
 2020-07-06 13:06:10 +08:00
Sebastien Bourdeauducq 6fa3a6bbd9 fix previous commit 2020-07-06 12:11:20 +08:00
Sebastien Bourdeauducq 7082e07a18 experiments: move BSS and stack to OCM3 2020-07-06 11:57:02 +08:00
Sebastien Bourdeauducq 21c0c5cbc8 Revert "simplify ps7_init" 
What the simplified ps7_init does can now be reproduced by the DDRC driver.
On the other hand, we are still experiencing crazy Zynq instability issues, so keep the original ps7_init around for debugging.

This reverts commit 9fcf9243f2.
 2020-07-06 11:55:04 +08:00
pca006132 90904634cd DDR: fixed register write. 
Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.
 2020-07-06 11:46:37 +08:00
Sebastien Bourdeauducq ae4d3e2455 smoltcp: enable IPv6 2020-07-06 11:30:48 +08:00
Sebastien Bourdeauducq 9fcf9243f2 simplify ps7_init 2020-07-06 00:52:40 +08:00
pca006132 90e33f688a FPU: moved enable function to zc706 2020-07-03 16:02:34 +08:00
Astro f0697c3ec3 ddr: implement additional configuration 2020-07-03 02:20:10 +02:00
Astro b2c707d543 ddr: remove superfluous `_reg` from register names 2020-07-03 02:20:10 +02:00
pca006132 6195ad40c3 libsupport_zynq: make panic handler an optional feature 2020-06-29 10:05:46 +08:00
Sebastien Bourdeauducq dd288912af fix experiments build for Cora 2020-06-28 17:47:33 +08:00
Astro ec252b099c experiments: don't write raw blocks to the sdcard by default 2020-06-26 23:27:28 +02:00
Astro a16c639eaf experiments: add bandwidth tester 2020-06-26 22:36:52 +02:00
Astro c6fa18344e uncached: disable cachable/bufferable 2020-06-26 22:32:49 +02:00
Astro 5c69bbdad6 mmu: fix L1Table.update() flush 2020-06-26 22:31:56 +02:00
Astro c0e66a632c ps7_init: move from experiments to libboard_zynq 2020-06-25 01:40:42 +02:00
Astro b129d3e0df panic: fix CORE_MASK 2020-06-25 01:27:23 +02:00
Astro 1e4be13869 experiments: implement ps7_init::apply() 2020-06-25 01:27:02 +02:00
Astro eea042e2ee experiments: update ps7_init for zc706 2020-06-24 22:23:05 +02:00
Astro b33ccf83ba eth: doc 2020-06-18 18:07:50 +02:00
Astro b4bcc6cf5c TcpStream: add send_slice() 2020-06-18 01:56:49 +02:00
Astro a80a2c67ef eth: put desc list behind UncachedSlice, invalidate buffers, add barriers 2020-06-18 01:28:29 +02:00
Astro d96343c249 uncached: refactor into UncachedSlice 2020-06-18 01:28:25 +02:00
Astro ae739146c5 cache: add the required barriers 2020-06-18 01:27:34 +02:00
Astro f50018092c mmu: add early memory barrier to L1Table.update() 2020-06-18 01:27:34 +02:00
Astro 7c4d390ce4 libcortex_a9: start Uncached 2020-06-18 01:27:34 +02:00
Astro 6761575b30 mmu: add L1Table.update() 2020-06-18 01:27:34 +02:00
Astro aebce435e2 mmu: switch bufferable=1 (writeback) for DDR pages 2020-06-18 01:27:34 +02:00
pca006132 98f5099684 removed newline character 2020-06-16 17:36:01 +08:00
pca006132 2c3fa991ad implemented display trait for errors 2020-06-16 17:36:01 +08:00
pca006132 2c14a2a1a2
fixed global timer reset 2020-06-16 17:31:37 +08:00
pca006132 191da7c959
Added Copy trait for Milliseconds struct. 2020-06-16 14:56:29 +08:00
pca006132 d52466cacf
DevC driver refactored. 2020-06-16 14:55:53 +08:00