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zynq-rs
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temporary debug bisect

This commit is contained in:
Simon Renblad 2024-10-15 15:40:40 +08:00
parent 5bd0fee4f7
commit d7fc183773
1 changed files with 6 additions and 0 deletions
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6
libboard_zynq/src/eth/mod.rs
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@ -350,6 +350,7 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> { impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
pub fn start_rx(self, rx_size: usize) -> Eth<GEM, rx::DescList, TX> { pub fn start_rx(self, rx_size: usize) -> Eth<GEM, rx::DescList, TX> {
info!("rx bisect 0");
let new_self = Eth { let new_self = Eth {
rx: rx::DescList::new(rx_size), rx: rx::DescList::new(rx_size),
tx: self.tx, tx: self.tx,
@ -357,15 +358,20 @@ impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
phy: self.phy, phy: self.phy,
idle: self.idle, idle: self.idle,
}; };
info!("rx bisect 1");
let list_addr = new_self.rx.list_addr(); let list_addr = new_self.rx.list_addr();
info!("rx bisect 2");
assert!(list_addr & 0b11 == 0); assert!(list_addr & 0b11 == 0);
info!("rx bisect 3");
GEM::regs().rx_qbar.write( GEM::regs().rx_qbar.write(
regs::RxQbar::zeroed() regs::RxQbar::zeroed()
.rx_q_baseaddr(list_addr >> 2) .rx_q_baseaddr(list_addr >> 2)
); );
info!("rx bisect 4");
GEM::regs().net_ctrl.modify(|_, w| GEM::regs().net_ctrl.modify(|_, w|
w.rx_en(true) w.rx_en(true)
); );
info!("rx bisect 5");
new_self new_self
} }