From d7fc1837734a4271b09dfc082ccfa2691b8be0a9 Mon Sep 17 00:00:00 2001
From: Simon Renblad <srenblad@m-labs.hk>
Date: Tue, 15 Oct 2024 15:40:40 +0800
Subject: [PATCH] temporary debug bisect

---
 libboard_zynq/src/eth/mod.rs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/libboard_zynq/src/eth/mod.rs b/libboard_zynq/src/eth/mod.rs
index 8dc0f62..9400958 100644
--- a/libboard_zynq/src/eth/mod.rs
+++ b/libboard_zynq/src/eth/mod.rs
@@ -350,6 +350,7 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
 
 impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
     pub fn start_rx(self, rx_size: usize) -> Eth<GEM, rx::DescList, TX> {
+        info!("rx bisect 0");
         let new_self = Eth {
             rx: rx::DescList::new(rx_size),
             tx: self.tx,
@@ -357,15 +358,20 @@ impl<GEM: Gem, RX, TX> Eth<GEM, RX, TX> {
             phy: self.phy,
             idle: self.idle,
         };
+        info!("rx bisect 1");
         let list_addr = new_self.rx.list_addr();
+        info!("rx bisect 2");
         assert!(list_addr & 0b11 == 0);
+        info!("rx bisect 3");
         GEM::regs().rx_qbar.write(
             regs::RxQbar::zeroed()
                 .rx_q_baseaddr(list_addr >> 2)
         );
+        info!("rx bisect 4");
         GEM::regs().net_ctrl.modify(|_, w|
             w.rx_en(true)
         );
+        info!("rx bisect 5");
         new_self
     }