srenblad
/
zynq-rs
forked from M-Labs/zynq-rs
1
0
Fork 0
Code Pull Requests Activity

eth: no unsafe, note, add qbar register fields

This commit is contained in:
Astro 2019-05-23 23:18:17 +02:00
parent 1033648c3e
commit 402b8c9ab1
2 changed files with 7 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/eth/mod.rs
View File

@ -8,15 +8,15 @@ pub struct Eth {
impl Eth {
pub fn gem0() -> Self {
let regs = unsafe { regs::RegisterBlock::gem0() };
let regs = regs::RegisterBlock::gem0();
Eth { regs }.init()
}
pub fn gem1() -> Self {
let regs = unsafe { regs::RegisterBlock::gem1() };
let regs = regs::RegisterBlock::gem1();
Eth { regs }.init()
}
fn init(self) -> Self {
// Clear the Network Control register.
self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
@ -39,6 +39,7 @@ impl Eth {
.tx_complete(true)
.tx_under_run(true)
.late_collision(true)
// not in the manual:
.hresp_not_ok(true)
);
// Disable all interrupts.

2
src/eth/regs.rs
View File

@ -144,8 +144,10 @@ register_bit!(rx_status, rx_overrun, 2);
register_bit!(rx_status, hresp_not_ok, 3);
register!(rx_qbar, RxQbar, RW, u32);
register_bits!(rx_qbar, rx_q_baseaddr, u32, 2, 31);
register!(tx_qbar, TxQbar, RW, u32);
register_bits!(tx_qbar, tx_q_baseaddr, u32, 2, 31);
register!(intr_dis, IntrDis, WO, u32);
register_bit!(intr_dis, mgmt_done, 0);