Sebastien Bourdeauducq b74d6fb9ba make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads		2017-03-27 16:32:23 +08:00
..
amp	firmware: don't build libdyld through misoc.	2017-03-14 08:33:31 +00:00
drtio	make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads	2017-03-27 16:32:23 +08:00
dsp	fir: streamline, optimize DSP extraction, left-align inputs	2016-12-20 21:39:51 +01:00
rtio	make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads	2017-03-27 16:32:23 +08:00
targets	rtio: Inout → InOut	2017-03-14 14:18:55 +08:00
test	gateware: reverse bytes of SDRAM word, not bits.	2017-03-17 11:16:46 +00:00
__init__.py	artiqlib -> artiq.gateware	2015-03-08 11:00:24 +01:00
ad9_dds.py	ad9xxx -> ad9_dds	2017-01-04 11:34:52 +01:00
ad9154_fmc_ebz.py	Merge remote-tracking branch 'm-labs/phaser2' into phaser2	2016-12-02 14:11:56 +01:00
nist_clock.py	gateware/nist_clock: increase DDS bus drive strength. Closes #468	2016-06-07 11:08:19 -04:00
nist_qc2.py	qc2: swap SPI/TTL, all TTL lines are now In+Out compatible	2016-05-19 10:42:03 +08:00
spi.py	spi: fix xfers with full data_width (closes #615)	2017-01-03 19:51:14 +01:00